ISO-CMOS MT8979
Pin Description (Continued)
Pin #
Name
Description
DIP PLCC
13 20
E8Ko
Extracted 8 kHz Clock (Output): An 8 kHz output generated by dividing the extracted
2048 kHz clock by 256 and aligning it with the received CEPT frame. The 8 kHz signal
can be used for synchronizing the system clock to the extracted 2048 kHz clock. Only
valid when device achieves synchronization (goes low during a loss of signal or a loss
of basic frame synchronization condition).
E8Ko goes high impedance when 8kHzSEL = 0 in MCW2.
15 23
XCtl
External Control (Output): An uncommitted external output pin which is set or reset
via bit 1 in Master Control Word 2 on CSTi0. The state of XCtl is updated once per
frame.
16 24
17 26
XSt
External Status: The state of this pin is sampled once per frame and the status is
reported in bit 1 of the Master Status Word 1 on CSTo.
CSTo
Control ST-BUS Output: A 2048 kbit/s serial control stream which provides the 16
signalling words, two Master Status Words, Phase Status Word and CRC Error Count.
18
NC
No Connection.
19 28
DSTi
Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the
30 PCM or data channels to be transmitted on the CEPT trunk.
20
NC
C2i
No Connection.
21 34
2048 kbit/s System Clock (Input): The master clock for the ST-BUS section of the
chip. All data on the ST-BUS is clocked in on the falling edge of the C2i and output on
the rising edge. The falling edge of C2i is also used to clock out data on the CEPT
transmit link.
22 37
23 38
TxMF
RxMF
Transmit Multiframe Boundary (Input): This input can be used to set the channel
associated and CRC transmitted multiframe boundary (clear the frame counters). The
device will generate its own multiframe if this pin is held high.
Received Multiframe Boundary (Output): An output pulse delimiting the received
Multiframe boundary. (This multiframe is not related to the received CRC multiframe.)
The next frame output on the data stream (DSTo) is received as frame 0 on the CEPT
link.
24
NC
E2i
No Connection.
25 40
Extracted 2048 kHz Clock (Input): The falling edge of this 2048 kHz clock is used to
latch the received data (RxD). This clock input must be derived from the CEPT
received data and must have its falling edge aligned with the center of the received bit
(RxD).
26 42
27 44
F0i
Frame Pulse Input: The ST-BUS frame synchronization signal which defines the
beginning of the 32 channel frame.
IC
Internal Connection: Tie to V (Ground) for normal operation.
SS
28
1
VDD
VSS
Positive Power Supply Input (+5 Volts).
Negative Power Supply Input (Ground).
14 6,8,
22
4-163
MITEL [ MITEL NETWORKS CORPORATION ]
