CMOS ST-BUS™ FAMILY
MT89L85
Enhanced Digital Switch
Advance Information
Features
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3.3 volt supply
5V tolerant inputs and TTL compatible outputs
256 x 256 channel non-blocking switch
Programmable frame integrity for wideband
channels
Automatic identification of ST-BUS/GCI
interface backplanes
Per channel tristate control
Patented message mode
Non-multiplexed microprocessor interface
Available in PLCC-44 and SSOP-48 packages
Pin compatible with MT8985 device
Low power consumption
DS5194
ISSUE 2
September 1999
Ordering Information
MT89L85AP 44 Pin PLCC
MT89L85AN 48 Pin SSOP
-40°C to +85°C
Description
The MT89L85 Enhanced Digital Switch device is an
upgraded 3-volt version of the MT8985 Digital
Switch. It is pin compatible with the MT8985 and
retains all of the MT8985's functionality. The
enhanced digital swtich is designed for switching
PCM-encoded voice or data, under microprocessor
control, in digital exchanges, PBXs and any ST-BUS/
MVIP environment. It provides simultaneous
connections for up to 256 64kb/s channels. Each of
the eight serial inputs and outputs consist of 32 64
kbit/s channels multiplexed to form a 2048 kbit/s
stream. As the main function in switching
applications, the device provides per-channel
selection between variable or constant throughput
delays. The constant throughput delay feature allows
grouped channels such as ISDN H0 to be switched
through the device maintaining its sequence
integrity. The MT89L85 is ideal for medium sized
mixed voice/data switch and voice processing
applications.
Applications
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Medium size digital switch matrices
Hyperchannel switching (e.g., ISDN H0)
ST-BUS/MVIP
™
interface functions
Serial bus control and monitoring
Centralized voice processing systems
Data multiplexer
C4i
F0i RESET V
DD
V
SS
**
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
Serial
to
Parallel
Converter
Data
Memory
Frame
Counter
Output
MUX
Parallel
to
Serial
Converter
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
Control Register
Connection
Memory
Control Interface
** for 48-pin SSOP only
DS CS R/W A5/
A0
DTA D7/
D0
CSTo
Figure 1 - Functional Block Diagram
1