Advance Information
Pin Description (continued)
Pin # Pin #
PLCC MQFP
12
6
Name
RSP
Description
MT9044
Receive Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing
pulse, which marks the end of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output).
This is an 8kHz 244ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is typically
used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 20.
Transmit Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
Frame Pulse (CMOS Output).
This is an 8kHz 122ns active high framing pulse,
which marks the beginning of a frame. See Figure 20.
Clock 1.544MHz (CMOS Output).
This output is used in T1 applications.
Analog Vdd.
+5V
DC
nominal.
Clock 3.088MHz (CMOS Output).
This output is used in T1 applications.
Clock 2.048MHz (CMOS Output).
This output is used for ST-BUS operation at
2.048Mb/s.
Clock 4.096MHz (CMOS Output).
This output is used for ST-BUS operation at
2.048Mb/s and 4.096Mb/s.
Clock 19.44MHz (CMOS Output).
This output is used in OC3/STS3 applications.
Analog PLL Clock Input (CMOS Input).
This input clock is a reference for an
internal analog PLL. This pin is internally pulled down to VSS.
Analog PLL Clock Output (CMOS Output).
This output clock is generated by
the internal analog PLL.
Clock 8.192MHz (CMOS Output).
This output is used for ST-BUS operation at
8.192Mb/s.
Clock 16.384MHz (CMOS Output).
This output is used for ST-BUS operation with
a 16.384MHz clock.
Clock 6.312 Mhz (CMOS Output).
This output is used for DS2 applications.
13
7
F0o
14
8
TSP
15
16
17
18
19
20
21
22
24
25
26
27
29
30
9
10
11
12
13
14
15
16
18
19
20
21
23
24
F8o
C1.5o
AVdd
C3o
C2o
C4o
C19o
ACKi
ACKo
C8o
C16o
C6o
HOLDOVER
Holdover (CMOS Output).
This output goes to a logic high whenever the digital
PLL goes into holdover mode.
GTi
Guard Time (Schmitt Input).
This input is used by the MT9044 state machine in
both Manual and Automatic modes. The signal at this pin affects the state changes
between Primary Holdover Mode and Primary Normal Mode, and Primary
Holdover Mode and Secondary Normal Mode. The logic level at this input is gated
in by the rising edge of F8o. See Tables 4 and 5.
Guard Time (CMOS Output).
The LOS1 input is gated by the rising edge of F8o,
buffered and output on GTo. This pin is typically used to drive the GTi input through
an RC circuit.
Secondary Reference Loss (TTL Input).
This input is normally connected to the
loss of signal (LOS) output signal of a Line Interface Unit (LIU). When high, the
SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs
control the MT9044 state machine when operating in Automatic Control. The logic
level at this input is gated in by the rising edge of F8o. This pin is internally pulled
down to VSS.
32
26
GTo
33
27
LOS2
3
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