MT9044
Advance Information
PRI
SEC
TRST
TCLR
TCK
VSS
TMS
RST
TDI
FS1
FS2
6 5 4 3 2 1 44 43 42 41 40
PRI
SEC
TRST
TCLR
TCLK
VSS
TMS
RST
TDI
FS1
FS2
44 43 42 41 40 39 38 37 36 35 34
39
38
37
36
35
34
33
32
31
30
29
VDD
OSCo
OSCi
VSS
F16o
RSP
F0o
TSP
F8o
C1.5o
AVDD
7
8
9
10
11
12
13
14
15
16
17
MT9044
TEST
RSEL
MS1
MS2
TDO
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER
VDD
OSCo
OSCi
VSS
F16o
RSP
F0o
TSP
F8o
C1.5o
AVDD
1
2
3
4
5
6
7
8
9
10
11
MT9044AL
33
32
31
30
29
28
27
26
25
24
23
TEST
RSEL
MS1
MS2
TDO
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
C3o
C2o
C4o
C19o
ACKi
VSS
ACKo
C8o
C16o
C6o
VDD
Figure 2 - Pin Connections
Pin Description
Pin # Pin #
PLCC MQFP
1,10, 39,4,17
23,31
,25
2
3
40
41
Name
V
SS
TCK
TCLR
Ground.
0 Volts.
Test Clock (TTL Input):
Provides the clock to the JTAG test logic. This pin is
internally pulled up to V
DD
.
TIE Circuit Reset (TTL Input):
A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a re-alignment of input phase with output
phase as shown in Figure 19. The TCLR pin should be held low for a minimum of
300ns. This pin is internally pulled down to VSS.
Test Reset (TTL Input):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin is internally pulled down to VSS.
Secondary Reference (TTL Input).
This is one of two (PRI & SEC) input
reference sources (falling edge) used for synchronization. One of three possible
frequencies (8kHz, 1.544MHzMHz, or 2.048MHz) may be used. The selection of
the input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi
control inputs (Automatic or Manual). This pin is internally pulled up to V
DD
.
Primary Reference (TTL Input).
See pin description for SEC. This pin is
internally pulled up to V
DD
.
Positive Supply Voltage.
+5V
DC
nominal.
Oscillator Master Clock (CMOS Output).
For crystal operation, a 20MHz crystal
is connected from this pin to OSCi, see Figure 10. For clock oscillator operation,
this pin is left unconnected, see Figure 9.
Oscillator Master Clock (CMOS Input).
For crystal operation, a 20MHz crystal is
connected from this pin to OSCo, see Figure 10. For clock oscillator operation, this
pin is connected to a clock source, see Figure 9.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output).
This is an 8kHz 61ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is typically
used for ST-BUS operation at 8.192 Mb/s. See Figure 20.
Description
4
5
42
43
TRST
SEC
6
7,28
8
44
1,22
2
PRI
V
DD
OSCo
9
3
OSCi
11
5
F16o
2
C3o
C2o
C4o
C19o
ACKi
VSS
ACKo
C8o
C16o
C6o
VDD
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