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MT9076AP 参数 Datasheet PDF下载

MT9076AP图片预览
型号: MT9076AP
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1 3.3V单芯片收发器 [T1/E1/J1 3.3V Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 160 页 / 413 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9076
T1/E1/J1 3.3V Single Chip Transceiver
Preliminary Information
Features
Combined T1/E1/J1 framer and LIU, with PLL
and 3 HDLCs
In T1/J1 mode the LIU can recover signals
attenuated by up to 43dB (7000ft of 22 AWG
cable)
In E1 mode the LIU can recover signals
attenuated by up to 43dB (2200m of 0.65mm
cable)
Low jitter digital PLL (intrinsic jitter < 0.02UI)
HDLCs can be assigned to any timeslot
Comprehensive alarm detection, performance
monitoring and error insertion functions
2.048Mbit/s or 8.192Mbit/s ST-BUS streams
Support for Inverse Mux for ATM (IMA)
Support for V5.1 and V5.2 Access Networks
3.3V operation with 5V tolerant inputs
Intel or Motorola non-multiplexed 8-bit
microprocessor port
JTAG boundary scan
DS5289
ISSUE 1
January 2000
Ordering Information
MT9076AP
68 Pin PLCC
MT9076AB
80 Pin LQFP
-40 to +85°C
Description
The MT9076 is a highly featured single chip solution
for terminating T1/E1/J1 trunks. It contains a long-
haul LIU, an advanced framer, a high performance
PLL, and 3 HDLCs.
In T1 mode, the MT9076 supports D4, ESF and
SLC-96 formats meeting the latest recommendations
including AT&T PUB43801, TR-62411; ANSI T1.102,
T1.403 and T1.408; Telcordia GR-303-CORE.
In E1 mode, the MT9076 supports the latest ITU-T
Recommendations including G.703, G.704, G.706,
G.732, G.775, G.796, G.823, G.964 (V5.1), G.965
(V5.2) and I.431. It also supports ETSI ETS 300 011,
ETS 300 166, ETS 300 233, ETS 300 324 (V5.1) and
ETS 300 347 (V5.2).
Applications
E1/T1 add/drop multiplexers
Access networks
Primary rate ISDN nodes
Digital Cross-connect Systems (DCS)
TxDL TxDLCLK
TxMF
TxAO TxB TxA
DSTi
CSTi
Tdi
Tdo
Tms
Tclk
Trst
ST-BUS
Interface
IEEE
1149.1
Transmit Framing, Error,
Test Signal Generation and Slip Buffer
Pulse
Generator
Line
Driver
TTIP
TRING
National
Bit Buffer
Jitter Attenuator
& Clock Control
CAS
Buffer
Clock,Data
Recovery
DG Loop
MT
Loop
ST Loop
RM
Loop
PL Loop
Microprocessor
Interface
IRQ
D7~D0
AC4
S/FR
BS/LS
OSC1
OSC2
Data Link,
HDLC0
HDLC1
R/W/WR
CS
DS/RD
DSTo
CSTo
Rx Equalizer
& Data Slicer
AC0
RTIP
RRING
ST-BUS
Interface
Receive Framing, Performance Monitoring,
Alarm Detection, 2 Frame Slip Buffer
RxDLCLK RxDL
RxMF
/TxFP
LOS
RxFP
Exclk
F0b
C4b
Figure 1 - MT9076 Functional Block
1