®
CMOS ST-BUS™ FAMILY
MT9079
Advanced Controller for E1
Features
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Meets applicable requirements of CCITT
G.704, G.706, G.732, G.775, G.796, I.431 and
ETSI ETS 300 011
HDB3, RZ, NRZ (fibre interface) and bipolar
NRZ line codes
Data link access and national bit buffers (five
bytes each)
Enhanced alarms, performance monitoring and
error insertion
Maskable interrupts for alarms, receive CAS bit
changes, exception conditions and counter
overflows
Automatic interworking between CRC-4 and
non-CRC-4 multiframing
Dual transmit and receive 16 byte circular
channel buffers
Two frame receive elastic buffer with controlled
slip direction indication and 26 channel
hysteresis (208 UI wander tolerance)
CRC-4 updating algorithm for intermediate path
points of a message-based data link application
ISSUE 2
May 1995
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Ordering Information
MT9079AC
40 Pin Ceramic DIP
MT9079AE
40 Pin Plastic DIP
MT9079AL
44 Pin QFP
MT9079AP
44 Pin PLCC
-40° to 85°C
Description
The MT9079 is a feature rich E1 (PCM 30, 2.048
Mbps) link framer and controller that meets the latest
CCITT and ETSI requirements.
The MT9079 will interface to a 2.048 Mbps
backplane and can be controlled directly by a
parallel processor, serial controller or through the
ST-BUS.
Extensive alarm transmission and reporting, as well
as exhaustive performance monitoring and error
diagnostic features make this device ideal for a wide
variety of applications.
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Applications
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Primary rate ISDN network nodes
Digital Access Cross-connect (DACs)
CO and PABX switching equipment interfaces
E1 add/drop multiplexers and channel banks
Test equipment and satellite interfaces
TxMF
RxMF
DSTi
DSTo
Transmit & Receive
Data
Interface
Frame MUX/DEMUX
2 Frame Rx
Elastic
Buffer With
Slip Control
PCM 30
(E1)
Link
Interface
TAIS
TxA
TxB
RxA
RxB
TxDL
RxDL
DLCLK
Data
Link
Buffer
National
Bit
Buffer
Dual 16
Byte Rx
Buffer
Dual 16
Byte Tx
Buffer
Performance
Monitoring &
Alarm
Control
Phase
Detector
÷
256
Circuit
Timing
E2i
E8Ko
Control
Port
Interface
(fig. 3)
Control
Interface
ABCD
Signal
Buffer
Test
Code
Gen.
V
DD
V
SS
IC
C4i/C2i
F0i
ST-BUS Timing
Circuit
Timing
to all registers
and counters
RESET
Figure 1 - Functional Block Diagram
4-237
MITEL [ MITEL NETWORKS CORPORATION ]
