MT90826
Quad Digital Switch
Advanced Information
Features
•
•
•
•
•
•
•
•
•
•
•
•
4,096
×
4,096 channel non-blocking switching
at 8.192 or 16.384 Mb/s
Per-channel variable or constant throughput
delay
Accept ST-BUS streams of 2.048Mb/s,
4.096Mb/s, 8.192Mb/s, or 16.384 Mb/s
Split Rate mode allows mix of two bit rates and
rate conversions
Automatic frame offset delay measurement for
ST-BUS input and output streams
Per-stream frame delay offset programming
Per-channel high impedance output control
Bit Error Monitoring on selected ST-BUS input
and output channels.
Per-channel message mode
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
3.3V local I/O with 5V tolerant inputs and TTL
compatible outputs
Medium and large switching platforms
CTI application
Voice/data multiplexer
Digital cross connects
WAN access system
Wireless base stations
V
DD
V
SS
TMS
TDI
TDO
TCK
DS5197
ISSUE 2
June 1999
Ordering Information
MT90826AL
MT90826AG
160 Pin MQFP
160 Pin PBGA
-40 to +85 C
Description
The MT90826 Quad Digital Switch has a non-
blocking switch capacity of 4,096 x 4,096 channels at
a serial bit rate of 8.192Mb/s or 16.384 Mb/s, 2,048 x
2,048 channels at 4.096Mb/s and 1024 x 1024
channels at 2.048Mb/s. The device has many
features that are programmable on a per stream or
per channel basis, including message mode, input
offset delay and high impedance output control.
The per stream input and output delay control is
particularly useful for managing large multi-chip
switches with a distributed backplane.
Operating in Split Rate mode allows for switching
between two groups of bit rate streams.
Applications
•
•
•
•
•
•
TRST
IC1
RESET
ODE
Test Port
STi0/FEi0
STi1/FEi1
•
•
•
STi31/FEi31
Serial
to
Parallel
Converter
Internal
Registers
Connection
Memory
Multiple Buffer
Data Memory
Output
MUX
Parallel
to
Serial
Converter
STo0
STo1
•
•
•
STo31
Timing
Unit
Microprocessor Interface
PLLV
DD
PLLV
SS
CLK F0i
IC2 IC3 DT1 AT1
DS
CS
R/W
A13-A0
DTA
D15-D0
Figure 1 - Functional Block Diagram
1
MITEL [ MITEL NETWORKS CORPORATION ]
