CMOS MT9085
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Not
Used
Serial Channel
Number
Stream
Address
OE - Output Enable
ME - Message Enable
Mode Control - DM-1 or DM-2
Figure 10 - Mapping of Data Memory and PAC Control Functions on Connection Memory Data Bits
4
3
2
1
0
4
3
2
1
0
Unused
Channel
Address
Stream
Address
Ex. Serial Stream 4, Channel 3 Corresponds to SMX Channel Number 100 (Hex 0064)
Figure 11 - Decoding SMX Channel Number from Serial Stream & Channel Address
1024 Switch Configuration
2048 Channel Digital Space-Time Switch
Application
applications where a master 16.384 MHz oscillator is
used for system timing, the C4i and F0i clocks could
be derived directly from it.
A 2048 channel serial time-space digital switch
design is illustrated in Figure 12.
The DFPo and DFPo generated by PAC #1a are
used to switch the mode of operation of the Data
Memory SMXs between Counter and External
modes and also serve as the frame pulse for the two
SMXs. Because DFPo and DFPo are complementary
signals, one of the two SMXs is operated in the
Counter mode while the second one is operated in
the External mode. The states of the other control
inputs, R/W and ODE, are changed accordingly.
The main switching function is accomplished using
three MT9080s (SMXs). Two SMXs function as the
data memory, while the third is operated in Connect
Memory mode. Refer to the SMX data sheet for
more information on this configuration. The Serial to
parallel conversion for 2048 channels is handled by
two PACs. PAC #1a and PAC #1b.
Both are
configured for 2.048 Mbit/s operation (2/4S=0). The
MCB input is tied low in both devices. The parallel
data bus on each of the devices will be actively
driven for one C16 clock period. The CKD input is
set low in one of the devices and set high in the
other. This will cause the output timing of the two
PACs to be off set by one C16 clock period.
Consequently, the parallel output of one device will
be disabled while the other is active.
The SMX configured as the Connection Memory, is
fed a frame pulse from PAC #1b. The phase
alignment of CFPo with respect to DFPo ensures
that timing requirements for proper operation of the
SMXs are met. Refer to the SMX data sheet for
more information on the timing requirements.
The maximum delay through the switch is two
frames. Channels are double buffered and frame
The parallel to serial conversion is also
integrity
is
maintained
for
all
switching
accomplished with two PACs.
Data from the
configurations.
common SMX parallel bus is clocked into each PAC
in alternate clock periods.
For more information, see Mitel’s Application Note
MSAN-135, “Design of Large Digital Switching
Matrices using the SMX/PAC“ (in this data book)
and Application Sheet MSAS-62 “16.384 MHz Clock
Generation for SMX/PAC“ (available from Mitel).
The timing source generates a 16.384 MHz clock
phase locked to a 4.096 MHz clock. The framing
signal input to PAC #1a at F0i should meet the
requirements specified in this data sheet. In some
2-135
MITEL [ MITEL NETWORKS CORPORATION ]
