MT90863
3V Rate Conversion Digital Switch
Advance Information
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2,048
×
512 and 512 x 512 switching among
backplane and local streams
Rate conversion between 2.048, 4.096 and
8.192Mb/s
Optioal sub-rate switch configuration for
2.048 Mb/s streams
Per-channel variable or constant throughput
delay
Compatible to HMVIP and H.100 specifications
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel message mode
Per-channel direction control
Per-channel high impedance output control
Non-multiplexed microprocessor interface
Connection memory block programming
3.3V local I/O with 5V tolerant inputs and
TTL-compatible outputs
IEEE-1149.1 (JTAG) Test Port
DS5034
ISSUE 3
March 1999
Ordering Information
MT90863AL1
MT90863AG1
128 Pin MQFP
144 Pin BGA
-40 to +85 C
Description
The MT90863 Rate Conversion Switch provides
switching capacities of 2,048
×
512 channels
between backplane and local streams, and 512 x
512 channels for local streams. The connected serial
inputs and outputs may have 32, 64 and 128 64kb/s
channels per frame with data rates of 2.048Mb/s,
4.096Mb/s and 8.192Mb/s respectively.
The MT90863 also offers a sub-rate switching
configuration which allows 2-bit wide 16kb/s data
channels to be switched within the device.
The device has features (such as: message mode;
input and output offset delay; direction control; and,
high
impedance
output
control)
that
are
programmable on per-stream or per-channel basis.
Applications
•
•
•
•
Medium and large switching platforms
CTI application
Voice/data multiplexer
Support ST-BUS, HMVIP and H.100 interfaces
ODE
STio0/
FEi0
STio15/
FEi15
STio16/
FEi16
STio23/
FEi23
STio24
STio31
C16i
F0i
C4i/C8i
Backplane
Interface
S/P
&
P/S
Converter
V
DD
V
SS
ODE
STo0
Multiple Buffer
Data Memory
(2,048 channels)
Local
Connection
Memory High/Low
(512 locations)
Output
Mux
Local
Interface
P/S
Converter
Multiple Buffer
Data Memory
(512 channels)
Local
Interface
Multiple Buffer
Data Memory
(512 channels)
S/P
Converter
STo11
STo12
STo13
STo15
STi0
STi11
STi12
STi13
STi15
RESET
IC1
IC2
Internal
Registers
Timing
Unit
Backplane
Connection
Memory
(2,048 locations)
Microprocessor Interface
Test Port
F0o C4o
DS CS R/W
A7-A0
DTA D15-D0
TMS TDI TDO TCK TRST
Figure 1 - Functional Block Diagram
1
MITEL [ MITEL NETWORKS CORPORATION ]
