Preliminary Information
BCLK
MT9126
ENB1
ENB2/F0od
B1
PCMi/o1
B2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
B3
PCMi/o2
B4
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
32 kb/s
ADPCM i/o
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
B1
B2
B3
B4
24 kb/s
1 2 3 x 1 2 3 x 1 2 3 x 1 2 3 x
ADPCM i/o
B1
B2
B3
B4
B1
B2
B3
B4
16 kb/s
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2
SEL = 0
SEL = 1
SEL for 16 kb/s only
Figure 4 - SSI 8-Bit Companded PCM Relative Timing
Notes:
S = 3 bits sign extension
BCLK
...
(2.048 MHz only)
µ−Law
is 13 bit 2’s complement data (bits 0 -12)
A-Law is 12 bit 2’s complement data (shifted left once and utilizing
bits 1 - 12, bit 0 not defined)
EN1
ENB1
ENB2/F0od
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
PCMi/o1
B1
B2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
PCMi/o2
32 kb/s
ADPCM i/o
24 kb/s
1234 1234 1234 1234
B3
1234 1234
B4
B1
B2
B3
B4
B3
B4
123x 123x 123x 123x
12 12 12 12 12 12 12 12
123x 123x
12 12 12 12
B B B B B B B B
ADPCMi/o
16 kb/s
1 2 3 4 1 2 3 4
AA
AA
SEL = 0
AA
SEL = 1
AA
AA
B B B B
1 2 3 4
SEL = 1
SEL for 16 kb/s only
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
Figure 5 - SSI 16-Bit Linear PCM Relative Timing
8-41
MITEL [ MITEL NETWORKS CORPORATION ]
