MT9160B/61B
Register Summary
Address
00
01
02
03
04
05
06
07y
Bit 7
RxINC
-
-
PDFDI
CEN
C
7
D
7
-
Bit 6
RxFG
2
-
-
PDDR
DEN
C
6
D
6
-
Bit 5
RxFG
1
-
-
RST
D8
C
5
D
5
-
Bit 4
RxFG
0
-
-
-
A/µ
C
4
D
4
-
Bit 3
TxINC
-
-
T
x
Mute
Smag/
ITU-T
C
3
D
3
Bit 2
TxFG
2
STG
2
-
R
x
Mute
CSL
2
C
2
D
2
Bit 1
Advance Information
Bit 0
TxFG
0
STG
0
DrGain
R
x
Bsel
CSL
0
C
0
D
0
-
Description
Gain Control
Register 1
Gain Control
Register 2
Path Control
Control
Register 1
Control
Register 2
C-Channel
Register
D-Channel
Register
Loop Back
TxFG
1
STG
1
-
T
x
Bsel
CSL
1
C
1
D
1
PCM/
loopen
-
ANALOG
Table 2 - 5V Multi-featured Codec Register Map
Gain Control Register 1
ADDRESS = 00h WRITE/READ VERIFY
Power Reset Value
1000 0000
RxINC RxFG
2
RxFG
1
RxFG
0
TxINC TxFG
2
TxFG
1
TxFG
0
7
6
5
4
3
2
1
0
Receive Gain
Setting (dB)
(default) 0
-1
-2
-3
-4
-5
-6
-7
RxFG
2
0
0
0
0
1
1
1
1
RxFG
1
0
0
1
1
0
0
1
1
RxFG
0
0
1
0
1
0
1
0
1
Transmit Gain
Setting (dB)
(default) 0
1
2
3
4
5
6
7
TxFG
2
0
0
0
0
1
1
1
1
TxFG
1
0
0
1
1
0
0
1
1
TxFG
0
0
1
0
1
0
1
0
1
RxFG
n
= Receive Filter Gain bit n
TxFG
n
= Transmit Filter Gain bit n
RxINC: When high, the receive path nominal gain is set to 0 dB. When low, this gain is -6.0 dB.
TxINC: When high, the transmit nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB.
Note: Bits marked "-" are reserved bits and should be written with logic "0"
89