MT9160B/61B
MT9160BS/BN
VBias
VRef
NC
PWRST
IC
A/µ/IRQ
VSSD
CS
NC
SCLK
DATA1
DATA2
Advance Information
MT9160BE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
M+
M-
VSSA
NC
HSPKR +
HSPKR -
VDD
CLOCKin
NC
STB/F0i
Din
Dout
VBias
VRef
NC
PWRST
IC
A/µ/IRQ
VSSD
CS
NC
SCLK
DATA1
DATA2
MT9161BE/BS/BN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
M+
M-
VSSA
NC
HSPKR +
HSPKR -
VDD
CLOCKin
STBd/FOod
STB/F0i
Din
Dout
VBias
VRef
PWRST
IC
A/µ/IRQ
VSSD
CS
SCLK
DATA1
DATA2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
M+
M-
VSSA
HSPKR +
HSPKR -
VDD
CLOCKin
STB/F0i
Din
Dout
20 PIN SOIC/SSOP
24 PIN PDIP
24 PIN PDIP/SOIC/SSOP
Figure 2 - Pin Connections
Pin Description
Pin # Pin #
20 Pin 24 Pin
1
2
3
4
5
1
2
4
5
6
Name
V
Bias
V
Ref
PWRST
IC
A/µ/IRQ
Description
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external
amplifiers. Connect 0.1
µF
capacitor to V
SSA,
Connect 1
µF
capacitor to Vref.
Reference Voltage for Codec (Output).
Nominally [(V
DD
/2)-1.9] volts. Used
internally. Connect 0.1
µF
capacitor to V
SSA,
Connect 1
µF
capacitor to VBias.
Power-up Reset (Input).
CMOS compatible input with Schmitt Trigger (active low).
Resets internal state of device.
Internal Connection.
Tie externally to V
SSD
for normal operation.
A/µ
- When internal control bit DEn = 0 this CMOS level compatible input pin
governs the companding law used by the filter/Codec;
µ-Law
when tied to V
SSD
and
A-Law when tied to V
DD
. Logically OR’ed with A/µ register bit.
IRQ
- When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
Digital Ground.
Nominally 0 volts.
Chip Select (Input).
This input signal is used to select the device for microport
data transfers. Active low. CMOS level compatible.
Serial Port Synchronous Clock (Input).
Data clock for microport. CMOS level
compatible.
Bidirectional Serial Data.
Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input CMOS level compatible.
Serial Data Receive.
In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.
Data Output.
A high impedance three-state digital output for 8 bit wide channel
data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent
with the rising edge of the bit clock during the timeslot defined by STB, or according
to standard ST-BUS timing.
Data Input.
A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.
6
7
8
9
7
8
10
11
V
SSD
CS
SCLK
DATA 1
10
12
DATA 2
11
13
D
out
12
14
D
in
80
MITEL [ MITEL NETWORKS CORPORATION ]
