MT9196
IDPC. During a valid read transfer from IDPC data
simultaneously clocked out by the micro is ignored
by IDPC.
All data transfers through the microport are two-byte
transfers requiring the transmission of a Command/
Address byte followed by the data byte written or
read from the addressed register. CS must remain
asserted for the duration of this two-byte transfer. As
COMMAND/ADDRESS
Preliminary Information
shown in Figures 5 and 6 the falling edge of CS
indicates to the IDPC that a microport transfer is
about to begin. The first 8 clock cycles of SCLK after
the falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 1
RECEIVE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
DATA 1
TRANSMIT
SCLK
y
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CS
y
Delays due to internal processor timing which are transparent to IDPC.
The IDPC:- latches received data on the rising edge of SCLK.
- outputs transmit data on the falling edge of SCLK.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D
7
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
5 bits - Addressing Data
2 bits - Unused
X
X
A
4
A
3
A
2
A
1
D
0
A
0
R/W
Figure 5 - Serial Port Relative Timing for Intel Mode 0
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 2
RECEIVE
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DATA 1
TRANSMIT
SCLK
y
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
y
Delays due to internal processor timing which are transparent to IDPC.
The IDPC:- latches received data on the rising edge of SCLK.
- outputs transmit data on the falling edge of SCLK.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D
7
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
5 bits - Addressing Data
2 bits - Unused
R/W
X
A
4
A
3
A
2
A
1
D
0
A
0
X
Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
7-136
MITEL [ MITEL NETWORKS CORPORATION ]
