CMOS
MT93L16
Low-Voltage Acoustic Echo Canceller
Preliminary Information
Features
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Contains two echo cancellers: 112ms acoustic
echo canceller + 16ms line echo canceller
Works with low cost voice codec. ITU-T G.711
or signed mag
µ/A-Law,
or linear 2’s comp
Each port may operate in different format
Advanced NLP design - full duplex speech with
no switched loss on audio paths
Fast re-convergence time: tracks changing
echo environment quickly
Adaptation algorithm converges even during
Double-Talk
Designed for exceptional performance in high
background noise environments
Provides protection against narrow-band signal
divergence
Howling prevention stops uncontrolled
oscillation in high loop gain conditions
Offset nulling of all PCM channels
Serial micro-controller interface
ST-BUS, GCI, or variable-rate SSI PCM
interfaces
User gain control provided for speaker path
(-24dB to +21dB in 3dB steps)
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DS5068
ISSUE3
July 1999
Ordering Information
MT93L16AQ
36 Pin QSOP
-40
°C
to + 85
°C
AGC on speaker path
Handles up to 0 dB acoustic echo return loss
and 0dB line ERL
Transparent data transfer and mute options
20 MHz master clock operation
Low power mode during PCM Bypass
Bootloadable for future factory software
upgrades
2.7V to 3.6V supply voltage; 5V-tolerant inputs
Applications
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Full duplex speaker-phone for digital telephone
Echo cancellation for video conferencing
Handsfree in automobile environment
Full duplex speaker-phone for PC
Limiter
Sin
MD1
NBSD
S
1
µ
/A-Law/
Linear
Offset
Null
+
+
-
S
2
ADV
NLP
Program
RAM
S
3
Program
ROM
Linear/
µ/A-Law
Micro
Interface
Sout
DATA1
DATA2
ACOUSTIC ECHO PATH
CONTROL
UNIT
Adaptive
Filter
Line ECho Path
PORT 1
PORT 2
Howling
Double
Talk
Detector
R
3
R
2
Adaptive
Filter
NBSD
R
1
Controller
MD2
Rout
L
inear/
µ
/A-Law
Limiter
SCLK
-24 -> +21dB
AGC
User
Gain
-
ADV
NLP
CS
+
+
Offset
Null
µ
/A-Law/
Linear
Rin
VDD
VSS
RESET
FORMAT
ENA2
ENA1
LAW
F0i
BCLK/C4i
MCLK
Figure 1 - Functional Block Diagram
1
MITEL [ MITEL NETWORKS CORPORATION ]
