SL1461SA
ABSOLUTE MAXIMUM RATINGS cont.
All voltages are referred to VEE at 0V
Characteristics
Conditions
Min.
Typ.
Max.
MP16 package thermal resistance,
chip to case
41
°C/W
Power consumption at 5.5V
ESD protection - pins 1 to 15
ESD protection - Pin 16
250
mW
kV
2
Mil-std-883 method 3015 class 1
Mil-std-883 method 3015 class 1
1.7
kV
+5V
1nF
C12
100nF
47 F
C4
AGC BIAS
AFC WINDOW ADJUST
RV2
2K
50K
R6
27K
RV1
C3
C1
47nF
4K7
C2
100nF
TP4
R1
1
2
3
4
5
6
7
8
16
D1
15
14
13
12
100pF
C11
R5
TP1
TP2
BB515
BB515
C5
1K2
470nF
C10
R2
5K1
R4
D2
11
10
TP3
100pF
1K2
VIDEO OUTPUT
C9
47 F
4n7
C6
9
R3
C7
4K7
1nF
1nF
C8
RF INPUT
Fig.3 Standard application circuit
FUNCTIONAL DESCRIPTION
The SL1461SA is a wideband PLL FM demodulator,
optimised for application in satellite receiver systems and
requiring a minimum external component count. It contains all
the elements required for construction of a phase locked loop
circuit, with the exception of tuning components for the local
oscillator, and an AFC detector circuit for generation of error
signal to correct for any frequency drift in the outdoor unit local
oscillator. A block diagram is contained in Fig. 2 and the typical
application in Fig. 3.
ensures optimum linearity and threshold performance, and
gives a good safety margin over the typical sensitivity of
-40dBm.
The output of the preamplifier is fed to the mixer section
which is of balanced design for low radiation. In this stage the
RF signal is mixed with the local oscillator frequency, which is
generatedby an on–board oscillator. The oscillator block uses
anexternalvaractortunedsustainingnetworkandisoptimised
for high linearity over the normal deviation range. A typical
frequency versus voltage characteristic for the oscillator is
containedinFig. 7. Theloopoutputisdesignedtocompensate
for first order temperature variation effects; the typical stability
is shown in Fig. 8
The output of the mixer is then fed to the loop amplifier
around which feedback is applied to determine loop transfer
characteristic. Feedbackcanbeappliedeitherindifferentialor
singleendedmode;iftheappropriatephasedetectorgainsare
assumedincalculatingloopfilters, bothmodesshouldgivethe
same loop response.
The internal pin connections are contained in Fig.6/6a
InnormalapplicationsthesecondsatelliteIFfrequencyof
typically 402 or 479.5MHz is fed to the RF preamplifier, which
has a working sensitivity of typically -40 dBm, depending on
application and layout. The preamplifier contains an RF level
detectcircuit, whichgeneratesanAGCsignalthatcanbeused
forcontrollingthegainoftheIFamplifierstages,somaintaining
a fixed level to the RF input of the SL1461SA, for optimum
threshold performance. The bias point of the AGC circuit can
be adjusted to cater for variation in AGC line voltage
requirement and device input power. The typical AGC curves
are shown in Fig. 9. It is recommended that the device is
operated with an input signal between -30 and -35dBm. This
The loop amplifier drives a 75Ω output impedance buffer
amplifier, which can either be connected to a 75Ω load or used
to drive a high input impedance stage giving greater linearity
and approximately 6dB higher demodulated signal output
level.
4
MITEL [ MITEL NETWORKS CORPORATION ]
