VP211
Layout And Grounding
As with all high speed A to D converters, careful
consideration must be given to the PCB layout. High
performance can be obtained from the VP211 by tying all
grounds to a solid low impedance ground plane. Separate
analog and digital ground planes with a single common link
under the device can also be used to help reduce the
amount of digital noise fed back into the analog section of the
converter.
The VP211 should be decoupled with low impedance
100nF ceramic capacitors close to the package pins to avoid
lead inductance effects and the decoupling on supply lines
should further be improved by using a 47µF tantalum
capacitor in parallel with a 100nF ceramic capacitor. If VCCA
is derived from VCCD, a small inductor should be used to
reduce digital noise on the analog power supply. Jitter and
noise on clock input pins must be minimised. Long clock
lines should therefore be avoided and all clock lines correctly
terminated. Cross talk of digital signals to the analog inputs
must also be prevented as sampling cross talk produces DC
offsets on the sampled data, for this reason analog inputs
should not be run next to clock or data lines. Device
connections to the ground plane should be as short as
possible.
CLKIN
50R
1.2µH
100n
1
2
3
4
100n
C
c
C
comp
28
27
26
25
A Channel
Data
5
6
7
8
VP211
24
23
22
21
100n
47µ
100n
VINA
50R
VCCA
47µ
100n
100n
VCCD
9
100n
C
c
C
comp
20
19
18
17
16
15
Analog Ground
Digital Ground
B Channel
Data
10
11
VINB
50R
100n
12
13
14
Fig.5 Applications diagram
Application Circuit
Fig.5 shows a typical applications circuit for the VP211.
The supply connections are made using separate low noise
digital and analog power supplies and VCCD is further
isolated from VCCO using a 1.2µH inductor.
The COMPA and COMPB pins must be decoupled to
reduce any ripple at low frequencies which may distort the
ADC driver amplifier output, (see Fig.2.) The decoupling
capacitor value is determined by the required low frequency
performance of the system and can be obtained from the
following equation.
A ripple voltage
≤
10mV is recommended for good
system performance, e.g. If the analog input frequency F
in
=
10KHz a value of 0.75µF is required for C
Comp
.
To ensure effective A.C. coupling at low input
frequencies, the coupling capacitors on pins 6 and 11 can be
calculated from the high pass filter corner frequency
equation,
F
c
=
1
2 x
π
x RC
C
Comp
=
75x10
- 6
F
in
x V
Ripple
where
F
c
= Lower -3dB corner frequency
(R = Input Resistance, 25K typ. - 20K min)
6
MITEL [ MITEL NETWORKS CORPORATION ]
