VP2612
Video Multiplexer
Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2
DS3511 - 3.0 June 1996
FEATURES
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Fully integrated H261 video multiplexer
Inputs data direct from VP2611 source coder
Output to X21 line buffers
Line rates from 64kbits/s up to 2Mbits/s
100 Pin Quad Flatpack
ASSOCIATED PRODUCTS
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VP2611 H.261 Encoder
VP2615 H.261 Decoder
VP2614 Video Demultiplexer
VP520S CIF/QCIF Converter
VP510 Colour Space Converter
The VP2612 Video Multiplexer forms part of the Mitel
Semiconductor chip-set for video conferencing, video
telephony, and multimedia applications. This chip set
implements the H261 standard for video compression for line
rates of between 64K and 2M bits per second. With a 27MHz
clock rate full CIF resolution images can be coded at a frame
rate of up to 30Hz.
The device contains all the elements necessary to
convert the run length coded data from the VP2611 source
coder into an H261 compatible bit stream. It also calculates
the differential motion vectors and macroblock addresses
from the absolute values received from the VP2611. These
values are variable length coded, and bit packed for temporary
storage in the transmission buffer. The size of this buffer can
be either 256Kbits or 512Kbits. Data from the transmission
buffer is output through an X21 compatible serial interface,
and consists of frames containing framing bits, data, and the
BCH (511,493) forward error correction code.
The system processor interface is used to write data for
PTYPE, PSPARE, GSPARE, and to select the source of
temporal reference. The interface can also be used to monitor
the pointers into the transmission buffer, so that the buffer
fullness can be controlled using proprietary software
algorithms. In addition to the bus interface, flags are supplied
which indicate the start of each macroblock, each FEC stuffed
frame, the number of bits per picture is reaching the allowable
maximum, and impending buffer overflow.
Fig. 1. VP2612 Video Multiplexer
MITEL [ MITEL NETWORKS CORPORATION ]
