MITSUBISHI LSIs
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC RAM
FAST PAGE MODE 4194304-BIT (262144-WORD BY BY 16-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs,
fabricated with the high performance CMOS process, and is ideal
for memory systems where high speed, low power dissipation, and
low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is small enough for
battery back-up application.
This device has 2CAS and 1W terminals with a refresh cycle of
512 cycles every 8.2ms.
PIN CONFIGURATION (TOP VIEW)
(5V)V
CC
DQ
1
DQ
2
DQ
3
DQ
4
(5V)V
CC
DQ
5
DQ
6
V
SS
(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)
DQ
12
DQ
11
DQ
10
DQ
9
NC
LCAS
UCAS
OE
A
8
A
7
A
6
A
5
A
4
V
SS
(0V)
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
FEATURES
Type name
M5M44260CXX-5,-5S
M5M44260CXX-6,-6S
M5M44260CXX-7,-7S
RAS
CAS
access access
time
time
(max.ns) (max.ns)
Address
OE
access
access
time
time
(max.ns) (max.ns)
Power
Cycle
dissipa-
time
tion
(min.ns) (typ.mW)
DQ
7
DQ
8 10
NC
11
NC
12
W
13
RAS
14
NC
15
A
0 16
A
1 17
A
2 18
A
3 19
50
60
70
13
15
20
25
30
35
13
15
20
90
110
130
625
550
475
XX=J,TP
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS Input level
5.5mW (Max)
CMOS Input level
550µW (Max) *
Operating power dissipation
M5M44260Cxx-5,-5S
688mW (Max)
M5M44260Cxx-6,-6S
605mW (Max)
M5M44260Cxx-7,-7S
523mW (Max)
Self refresh capability *
Self refresh current
150µA (Max)
Extended refresh capability
Extended refresh current
150µA (Max)
Fast-page mode (512-column random access), Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, LCAS / UCAS and OE to control output buffer
impedance
512 refresh cycles every 8.2ms (A
0
~A
8
)
512 refresh cycles every 128ms (A
0
~A
8
) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S
: option) only
(5V)V
CC
20
Outline 40P0K (400mil SOJ)
(5V)V
CC
DQ
1
DQ
2
DQ
3
DQ4
(5V)V
CC
DQ
5
DQ
6
DQ
7
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
V
SS
(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8 10
APPLICATION
Microcomputer memory, Refresh memory for CRT
NC
13
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A
8
A
7
A
6
A
5
A
4
V
SS
(0V)
PIN DESCRIPTION
Pin name
A
0
~A
8
DQ
1
~DQ
16
RAS
LCAS
UCAS
W
OE
V
CC
V
SS
1
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
Upper byte control
column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
NC
14
W
15
RAS
16
NC
17
A
0 18
A
1 19
A
2 20
A
3 21
(5V)V
CC 22
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC: NO CONNECTION
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
