MITSUBISHI LSIs
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
PIN CONFIGURATION (TOP VIEW)
(3.3V)V
CC
DQ
1
DQ
2
DQ
3
DQ4
(3.3V)V
CC
DQ
5
DQ
6
DQ
7
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
S
S(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)
DQ
12
DQ
11
DQ
10
DQ
9
NC
LCAS
UCAS
OE
A
8
A
7
A
6
A
5
A
4
V
SS
(0V)
DQ
8 10
FEATURES
Type name
M5M4V4265CXX-5,-5S
M5M4V4265CXX-6,-6S
M5M4V4265CXX-7,-7S
RAS
CAS
Address
access
access access
time
time
time
(max.ns) (max.ns) (max.ns)
Power
OE
Cycle
dissipa-
access
time
tion
time
(max.ns) (min.ns) (typ.mW)
NC
11
NC
12
W
13
RAS
14
NC
15
A
0 16
A
1 17
A
2 18
A
3 19
(3.3V)V
CC 20
50
60
70
13
15
20
25
30
35
13
15
20
90
110
130
408
363
333
XX=TP,J
Standard 40 pin SOJ, 44 pin TSOP (II)
Single 3.3±0.3V supply
Low stand-by power dissipation
CMOS Input level
1.8mW (Max)
CMOS Input level
360µW (Max) *
Operating power dissipation
M5M4V4265CXX-5,-5S
486mW (Max)
M5M4V4265CXX-6,-6S
432mW (Max)
M5M4V4265CXX-7,-7S
396mW (Max)
Self refresh capability *
Self refresh current
100µA (Max)
Extended refresh capability
Extended refresh current
100µA (Max)
EDO mode (512-column random access), Read-modify-write, RAS-
only refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A
0
~A
8
)
512 refresh cycles every 128ms (A
0
~A
8
) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
-7S : option) only
Outline 40P0K (400mil SOJ)
(3.3V)V
CC
DQ
1
DQ
2
DQ
3
DQ4
(3.3V)V
CC
DQ
5
DQ
6
DQ
7
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
V
S
S(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8 10
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
memory for CRT
NC
13
NC
14
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A
8
A
7
A
6
A
5
A
4
V
SS
(0V)
PIN DESCRIPTION
Pin name
A
0
~A
8
DQ
1
~DQ
16
RAS
LCAS
UCAS
W
OE
V
CC
V
SS
1
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
Upper byte control
column address strobe input
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
W
15
RAS
16
NC
17
A
0 18
A
1 19
A
2 20
A
3 21
(3.3V)V
CC 22
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC : NO CONNECTION
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
