MITSUBISHI LSIs
1998.11.30 Ver..B
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
M5M54R08AJ-10,-12,-15
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
PIN CONFIGURATION (TOP VIEW)
DESCRIPTION
The M5M54R08AJ is a family of 524288-word by 8-bit
static RAMs, fabricated with the high performance CMOS
silicon gate process and designed for high speed
application.
These devices operate on a single 3.3V supply, and are
directly TTL compatible. They include a power down
feature as well.
FEATURES
•Fast access time
M5M54R08AJ-10
...
10ns(max)
M5M54R08AJ-12
...
12ns(max)
M5M54R08AJ-15
...
15ns(max)
•Single +3.3V power supply
•Fully static operation : No clocks, No refresh
•Common data I/O
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
A
0
A
1
address
A
2
inputs
A
3
A
4
chip select
S
input
DQ
1
data inputs/
outputs
DQ
2
(3.3V)
V
CC
(0V)
GND
data
DQ
3
inputs/
outputs
DQ
4
write control
W
input
A
5
A
6
address
A
7
inputs
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A
18
A
17
address
inputs
A
16
A
15
output enable
OE
input
data
DQ
8
inputs/
DQ
7
outputs
GND
(0V)
V
CC
(3.3V)
DQ
6
data
inputs/
DQ
5
outputs
A
14
A
13
A
12
A
11
address
inputs
A
10
NC
Outline
36P0K (SOJ)
APPLICATION
High-speed memory units
PACKAGE
M5M54R08AJ
: 36pin 400mil SOJ
BLOCK DIAGRAM
A
0
A
1
A
2
address
A
4
inputs
1
2
3
4
5
MEMORY ARRAY
1024 ROWS
4096 COLUMNS
7
8
11
12
25
26
29
30
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
data
inputs/
outputs
A
3
A
5
14
A
6
15
A
7
16
A
8
17
A
9
18
COLUMN I/O CIRCUITS
S
6
COLUMN ADDRESS
COLUMN
DECODERS
ADDRESS
9
27
10
28
W
13
DECODERS
COLUMN INPUT BUFFERS
VCC (3.3V)
OE 31
GND (0V)
20 21 22 23 24 32 33 34 35
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
16
A
17
address inputs
MITSUBISHI
ELECTRIC
1
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
