MITSUBISHI
〈DIGITAL
ASSP〉
MITSUBISHI
〈DIGITAL
ASSP〉
M66252P/FP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
1152 x 8-BIT LINE MEMORY (FIFO)
DESCRIPTION
The M66252P/FP is a high-speed line memory with a FIFO
(First In First Out) structure of 1152-word
×
8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read and is most suitable as a buffer memory between
devices with different data processing throughput.
FEATURES
• Memory construction ........................................................
............................. 1152words x 8bits (dynamic memory)
• High-speed cycle ............................................ 50ns (min.)
• High-speed access ........................................ 40ns (max.)
• Output hold ....................................................... 5ns (min.)
• Fully independent, asynchronous write and read opera-
tions
• Variable-length delay bit
• Output .................................................................... 3-state
APPLICATION
Digital photocopiers, high-speed facsimiles, laser beam print-
ers.
PIN CONFIGURATION (TOP VIEW)
Q
0
Q
1
Data output
Q
2
Q
3
Read enable input
RE
Read reset input RRES
GND
Read clock input RCK
Q
4
Q
5
Data output
Q
6
Q
7
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
D
0
D
1
D
2
D
3
WE
WRES
V
CC
WCK
D
4
D
5
D
6
D
7
Data input
Outline 24P4Y
24P2W-A
M66252P/FP
Write enable input
Write reset input
Write clock input
Data input
BLOCK DIAGRAM
�½
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
24 23 22 21 16 15 14 13
Input buffer
Write
reset input WRES 19
Write
clock input WCK 17
Memory array
(1152 x 8 bits)
Read control circuit
Write control circuit
Write
enable input WE 20
Read address counter
Write address counter
�½
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
1 2 3 4 9 10 11 12
Output buffer
Data input
Data output
5 RE Read input
enable
6 RRES Read input
reset
8 RCK Read input
clock
Vcc 18
7 GND
1
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
