MITSUBISHI
〈DIGITAL
ASSP〉
MITSUBISHI
〈DIGITAL
ASSP〉
M66256FP
M66256FP
5120
×
8-BIT LINE MEMORY (FIFO)
5120
×
8-BIT LINE MEMORY (FIFO)
DESCRIPTION
The M66256FP is a high-speed line memory with a FIFO
(First In First Out) structure of 5120-word
×
8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between de-
vices with different data processing throughput.
FEATURES
• Memory configuration ........................................................
............................. 5120 words
×
8-bits (dynamic memory)
• High-speed cycle ............................................. 25ns (Min.)
• High-speed access ......................................... 18ns (Max.)
• Output hold ........................................................ 3ns (Min.)
• Fully independent, asynchronous write and read operations
• Variable length delay bit
• Output .................................................................... 3 states
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam print-
ers.
PIN CONFIGURATION (TOP VIEW)
Q
0
←
1
Q
1
←
2
DATA OUTPUT
Q
2
←
3
Q
3
←
4
READ ENABLE INPUT
RE
→
5
24
←
D
0
23
←
D
1
22
←
D
2
21
←
D
3
20
←
WE
WRITE ENABLE INPUT
DATA INPUT
M66256FP
READ RESET INPUT RRES
→
6
GND
7
READ CLOCK INPUT RCK
→
8
Q
4
←
9
Q
5
←
10
DATA OUTPUT
Q
6
←
11
Q
7
←
12
19
←
WRES WRITE RESET INPUT
18
V
CC
17
←
WCK WRITE CLOCK INPUT
16
←
D
4
15
←
D
5
14
←
D
6
13
←
D
7
DATA INPUT
Outline 24P2U-A
BLOCK DIAGRAM
DATA INPUT
D
0
~ D
7
13 14 15 16 21 22 23 24
DATA OUTPUT
Q
0
~ Q
7
1 2 3 4 9 10 11 12
INPUT BUFFER
OUTPUT BUFFER
READ ADDRESS COUNTER
WRITE ADDRESS COUNTER
WRITE CONTROL CIRCUIT
WRITE
ENABLE INPUT WE 20
WRITE
RESET INPUT WRES 19
WRITE
CLOCK INPUT WCK 17
READ CONTROL CIRCUIT
5 RE
READ
ENABLE INPUT
MEMORY ARRAY OF
5120-WORD
×
8-BIT
CONFIGURATION
READ
6 RRES RESET INPUT
READ
8 RCK CLOCK INPUT
V
CC
18
7 GND
1