MITSUBISHI
〈DIGITAL
ASSP〉
MITSUBISHI
〈DIGITAL
ASSP〉
M66257FP
M66257FP
5120
×
8-BIT 2 LINE MEMORY (FIFO)
5120
×
8-BIT
×
2
×
LINE MEMORY (FIFO)
DESCRIPTION
The M66257FP is a high-speed line memory with a FIFO
(First In First Out) structure of 5120-word
×
8-bit double con-
figuration which uses high-performance silicon gate CMOS
process technology.
It allows simultaneous output of 1-line delay data and 2-line
delay data, and is most suitable for data correction over mul-
tiple lines.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between de-
vices with different data processing throughput.
FEATURES
• Memory configuration of 5120 words
×
8 bits
×
2 (dynamic
memory)
• High-speed cycle ............................................. 25ns (Min.)
• High-speed access ......................................... 18ns (Max.)
• Output hold ........................................................ 3ns (Min.)
• Fully independent, asynchronous write and read operations
• Output .................................................................... 3 states
• Q
00
to Q
07
........................................................ 1-line delay
• Q
10
to Q
17
........................................................ 2-line delay
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam print-
ers.
PIN CONFIGURATION (TOP VIEW)
GND
1
36
V
CC
READ ENABLE INPUT
READ RESET INPUT
READ CLOCK INPUT
WRITE ENABLE INPUT
WRITE RESET INPUT
WRITE CLOCK INPUT
Q
00
←
2
Q
01
←
3
Q
02
←
4
Q
03
←
5
Q
04
←
6
Q
05
←
7
Q
06
←
8
DATA OUTPUT
Q
07
←
9
Q
10
←
10
Q
11
←
11
Q
12
←
12
Q
13
←
13
Q
14
←
14
Q
15
←
15
Q
16
←
16
Q
17
←
17
V
CC
18
35
←
RE
34
←
RRES
33
←
RCK
32
←
WE
31
←
WRES
30
←
WCK
Outline 36P2R-A
M66257FP
29
28
GND
V
CC
27
←
D
0
26
←
D
1
25
←
D
2
24
←
D
3
23
←
D
4
22
←
D
5
21
←
D
6
20
←
D
7
19
GND
DATA INPUT
BLOCK DIAGRAM
DATA INPUT
D
0
~
D
7
27 26 25 24 23 22 21 20
DATA OUTPUT
Q
00
~
Q
07
DATA OUTPUT
Q
10
~
Q
17
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
INPUT BUFFER
OUTPUT BUFFER
WRITE ADDRESS COUNTER
READ ADDRESS COUNTER
WRITE CONTROL CIRCUIT
READ CONTROL CIRCUIT
WRITE
ENABLE INPUT
WE 32
35 RE
READ
ENABLE INPUT
WRITE
RESET INPUT WRES 31
WRITE
CLOCK INPUT
MEMORY ARRAY OF
5120-WORD
×
8-BIT
×
2 CONFIGURATION
1-LINE DELAY DATA ONLY MEMORY/
2-LINE DELAY DATA ONLY MEMORY
READ
34 RRES RESET INPUT
READ
CLOCK INPUT
WCK 30
33 RCK
V
CC
18
V
CC
28
V
CC
36
1 GND
19 GND
29 GND
1
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