MITSUBISHI <DIGITAL ASSP>
M66258FP
8192 x 8-BIT LINE MEMORY
DESCRIPTION
The M66258FP is high speed line memory that uses high
performance silicon gate CMOS process technology and adopts
the FIFO (First In First Out) structure consisting of 8192 words x 8
bits.
The M66258FP, performing reading and writing operations at
different cycles independently and asynchronously, is optimal for
buffer memory to be used between equipment of different data
processing speeds.
PIN CONFIGURATION (TOP VIEW)
Q0
Q1
DATA OUTPUT
Q2
Q3
READ ENABLE
RE
INPUT
READ RESET
RRES
INPUT
GND
READ CLOCK
INPUT
RCK
Q4
DATA OUTPUT
1
2
3
4
5
6
7
8
9
24 D0
23 D1
22 D2
21 D3
WRITE ENABLE
INPUT
19 WRES WRITE RESET
INPUT
20 WE
18 V
CC
17 WCK
16 D4
15 D5
DATA INPUT
14 D6
13 D7
WRITE CLOCK
INPUT
DATA INPUT
FEATURES
•
•
•
•
•
Memory configuration
8192 words x 8 bits configuration
High speed cycle
20 ns (Min.)
High speed access
16 ns (Max.)
Output hold
3 ns (Min.)
Reading and writing operations can be completely carried out
independently and asynchronously.
• Variable length delay bit
• Input/output
TTL direct connection allowable
• Output
3 states
M66258FP
Q5 10
Q6 11
Q7 12
APPLICATION
• Digital copying machine, laser beam printer, high speed facsimile,
etc.
Outline 24P2U-A(SSOP)
FUNCTIONAL DESCRIPTION
When write enable input WE is set to "L", the contents of data
inputs D0 to D7 are read in synchronization with a rising edge of
write lock input WCK to perform writing operation. When this is the
case,the write address counter is also incremented simultaneously.
When WE is set to "H", the writing operation is inhibited and the
write address counter stops.
When write reset input WRES is set to "L", the write address
counter is initialized.
When read enable input RE is set to "L", the contents of memory
are output to data outputs Q0 to Q7 in synchronization with a rising
edge of read clock input RCK to perform reading operation. When
this is the case, the read address counter is incremented
simultaneously.
When RE is set to "H", the reading operation is inhibited and the
read address counter stops. The outputs are placed in a high
impedance state.
When read reset input RRES is set to "L", the read address
counter is initialized.
1
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
