MITSUBISHI
〈DIGITAL
ASSP〉
MITSUBISHI
〈DIGITAL
ASSP〉
M66260FP
M66260FP
8
×
4 CROSSPOINT SWITCH MIXING FUNCTION
8
×
4 CROSSPOINT SWITCH withwith MIXING FUNCTION
DESCRIPTION
The M66260 is an integrated circuit consisiting of a 8
×
4
cross point switch capable of selecting 32 analog switches
with mixing registance respectively by serial control inputs.
Using the M66260 with an external standard Op-Amp, 8 ana-
log input signals can be mixed and output to any of 4 outputs
freely by serial control inputs.
FEATURES
• Serial data input type
• Switching and mixing function possible with standard Op-
Amp.
• Switch matrix can be extended to 8
×
8 or 8
×
12 by com-
bining 2 or 3 ICs in parallel.
• Excellent crosstalk characteristic
.......................... –90 dB [f = 3 kHz, V
IN
= –10dBV] (typ.)
APPLICATION
Line switching with mixing function of telephone and commu-
nication equipments.
FUNCTION
Serial data input A is the data input of the first step of 32 BIT
SHIFT REGISTER and when latch enable input LE is “L”, the
signal of A shifts shifting registers one by one when shift
clock input CKs changes from “L” to “H”, in units of 32 bits.
PIN CONFIGURATION (TOP VIEW)
CK
S
→
1
A
→
2
DIRECT-CONNECTED
R
D
→
3
RESET INPUT
X
0
→
4
X
2
→
5
SWITCH INPUT
X
4
→
6
X
6
→
7
Y
OUT0
←
8
Y
S0
←
9
SWITCH OUTPUT
Y
S1
←
10
Y
OUT1
←
11
GND
12
SHIFT DATA INPUT
SHIFT CLOCK INPUT
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
→
SQ31
SHIFT DATA OUTPUT
←
LE
LATCH ENABLE INPUT
←
X
1
←
X
3
SWITCH INPUT
←
X
5
�½
←
X
7
→
Y
OUT3
→
Y
S3
SWITCH OUTPUT
→
Y
S2
�½
→
Y
OUT2
V
CC
Outline 24P2N-B
The 32 bits are stored into LATCH CIRCUIT in parallel when
latch enable LE changes from “L” to “H”.
Analog switches come on in a low-impedance state when
the output of the corresponding latch circuit is “H”. They
come off in a high-impedance stage when the output of the
corresponding circuit is “L”.
M66260FP
BLOCK DIAGRAM
DIRECT
RESET INPUT
SWITCH INPUTS
X
4
X
3
6
20
LATCH ENABLE
INPUT
CK
S
R
D
LE
1
3
22
SHIFT CLOCK
INPUT
SHIFT DATA
INPUT
A
2
X
7
18
Y
OUT0
Y
S0
Y
OUT1
Y
S1
Y
OUT2
Y
S2
Y
OUT3
Y
S3
8
X
6
7
X
5
19
X
2
5
X
1
21
X
0
4
7
9
11
6
5
4
3
2
1
0
SWITCH OUTPUTS
R
Q
L0
Q
L1
Q
L2
Q
L3
Q
L4
LE
D
L0
D
L1
D
L2
D
L3
D
L4
CK
Q
S0
Q
S1
Q
S2
Q
S3
Q
S4
D
IN
15
10
14
14
13
12
11
10
9
8
LATCH
CIRCUIT
(×
32)
32-BIT
SHIFT
REGISTER
Note 1:
n
Q
Ln
23
15
17
22
21
20
19
18
17
16
Q
L30
Q
L31
31
16
13
12
GND V
CC
30
29
28
27
26
25
24
D
L30
D
L31
Q
S30
Q
S31
n = 0~31
23
SQ
31
SHIFT DATA OUTPUT
24
V
CC
1
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