PST3433 参数 Datasheet PDF下载

MITSUMI

CMOS System Reset PST3XXX

Description of Operation

(1) V

DD

> VS, V

OUT

: H (M1: ON, M2, M3: OFF)

When V

DD

is gradually lowered from the above state, detection voltage is as follows.

Detection voltage: (R1 + R2 + R3) / (R2 + R3) VREF

(2) V

DD

< VS, V

OUT

: L (M1: OFF, M2, M3: ON)

When V

DD

is gradually raised from the above state, release voltage is as follows.

Release voltage = (R1 + R2) / (R2) VREF

(3) Hysteresis voltage = (release voltage) - (detection voltage).

(4) When V

DD

drops and goes below the minimum operating voltage, output is undefined; when output is

pulled up, output becomes V

DD

.

(5) VREF and detection resistors

1) The reference voltage source (VREF) for this IC is 0.8V typ. This gives excellent low power consumption

and temperature characteristics.

2) The high resistance process is used for resistors R1, R2 and R3 to achieve low consumption current for

the IC.

(6) Through current flows momentarily for detection and release. When using high V

DD

pin impedance, the

through current may cause oscillation.

(Example) Detection voltage changed by external settings

*

The IC input voltage fluctuates due to the

*

through current R11 voltage drop, and

an oscillation state where detection and

release are repeated may occur.

With CMOS output types, do not use as

shown in the diagram at left.