MOSA
Acknowledge
MS6260
Gain And Attenuation Volume Controller IC
During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral
(audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that
the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.
SCL
1
2
3
7
8
9
SDA
MSB
Start
Acknowledge
The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise,
the SDA line will remain at the HIGH level during the ninth (9
th
) clock pulse. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
Timing of SDA and SCL bus lines
SDA
t
f
SCL
t
LOW
t
r
t
SU;DAT
t
f
t
HD;STA
t
SP
t
r
t
BUF
S
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;STA
S
r
t
SU;STO
P
S
Standard mode
Symbol
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
BUF
C
b
V
nL
V
nH
Parameter
Min
0
4.0
4.7
4.0
4.7
0
250
-
-
4.0
4.7
-
Max
100
-
-
-
-
3.45
-
1000
300
-
-
400
-
-
Unit
kHz
us
us
us
us
us
ns
ns
ns
us
us
pF
V
V
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time:
For I
2
C-bus devices
Data-set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the LOW level for each connected device (including
0.1V
DD
hysteresis)
Noise margin at the HIGH level for each connected device (including
0.2V
DD
hysteresis)
REV 3
6
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