MOSA
Timing of SDA and SCL Bus Lines
SDA
t
f
SCL
MS6714
4 Stereo Inputs / 2 Channels Output Audio Processor
t
LOW
t
r
t
SU;DAT
t
f
t
HD;STA
t
SP
t
r
t
BUF
S
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;STA
S
r
t
SU;STO
P
S
Standard Mode
Symbol
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
BUF
C
b
V
nL
V
nH
Parameter
Min
0
4.0
4.7
4.0
4.7
0
250
-
-
4.0
4.7
-
Max
100
-
-
-
-
3.45
-
1000
300
-
-
400
-
-
Unit
kHz
us
us
us
us
us
ns
ns
ns
us
us
pF
V
V
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time:
For I
2
C-bus devices
Data-set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the LOW level for each connected device (including
0.1V
DD
hysteresis)
Noise margin at the HIGH level for each connected device (including
0.2V
DD
hysteresis)
BUS INTERFACE
Data are transmitted to and from the MCU to the MS6714 via the SDA and SCL. The SDA and SCL make up the
BUS interface. It should be noted that pull-up resistors must be connected to the positive supply voltage.
V
DD
Rp
Rp
Pull up resistors
SDA (Serial Data Line)
SCL (Serial Clock Line)
MCU
MS6714
REV1.0
8
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MOSA [ MOSA ELECTRONICS ]
