MS6714
MOSA
4 Stereo Inputs / 2 Channels Output Audio Processor
Timing of SDA and SCL Bus Lines
SDA
t
f
tSU;DAT
t
LOW
t
BUF
tf
t
r
t
r
tHD;STA
tSP
SCL
tHD;STA
t
SU;STA
t
SU;STO
t
HIGH
S
t
HD;DAT
Sr
P
S
Standard Mode
Symbol
Min
Max
Unit
Parameter
fSCL
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
0
100
kHz
tHD:STA
4.0
-
us
tLOW
LOW period of the SCL clock
4.7
4.0
4.7
-
-
-
us
us
us
tHIGH
tSU:STA
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time:
tHD:DAT
0
3.45
us
For I2C-bus devices
tSU:DAT
tr
Data-set-up time
250
-
-
1000
300
-
ns
ns
ns
us
us
pF
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
tf
-
tSU:STO
tBUF
Cb
4.0
4.7
-
Bus free time between a STOP and START condition
Capacitive load for each bus line
-
400
Noise margin at the LOW level for each connected device (including
hysteresis)
VnL
VnH
0.1VDD
0.2VDD
-
-
V
V
Noise margin at the HIGH level for each connected device (including
hysteresis)
BUS INTERFACE
Data are transmitted to and from the MCU to the MS6714 via the SDA and SCL. The SDA and SCL make up the
BUS interface. It should be noted that pull-up resistors must be connected to the positive supply voltage.
VDD
Rp
Rp
Pull up resistors
SDA (Serial Data Line)
SCL (Serial Clock Line)
MCU
MS6714
REV1.0
8
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MOSA [ MOSA ELECTRONICS ]
