Write Cycle 1
10,11
(/WE Controlled)
t
WC
t
AW
Address
t
AH
t
WP
/WE
t
AS
t
DW
D
IN
t
WZ
D
OUT
Data Valid
t
OW
t
DH
Notes
1 During V
CC
power-up, a pull-up resistor to V
CC
on /CS is required to meet I SB specification.
2 This parameter is sampled and not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, C.
4 t
CLZ
and t
CHZ
are specified with CL = 5pF as in Figure C. Transition is measured ±500mV
from steady-state voltage.
5 This parameter is guaranteed but not tested.
6 /WE is HIGH for read cycle.
7 /CS and /OE are LOW for Read cycle.
8 Address valid prior to or coincident with CS transition LOW.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 /CS or /WE must be HIGH during address transitions.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
PAGE 7
Issue 5.1 April 2001
MOSAIC [ MOSAIC ]
