Capacitance
(V
CC
= 5.0V, T
A
= 25
O
C)
P aram eter
Input C apacitan ce, (
Address, /O E, /W E)
Input C apacitan ce, (
O ther)
O utpu t C apacita nce,
8 bit m ode (w orst case)
S ym b ol
C
IN 1
C
IN 2
C
I/O
T est C ondition
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
M in
-
-
-
T yp
-
-
-
M ax
32
7
40
U nit
pF
pF
pF
Note : These Parameters are calculated not measured.
Test Conditions
•
•
•
•
•
Input pulse levels : 0V to 3.0V
Input rise and fall times : 3ns
Input and Output timing reference levels : 1.5V
Output Load : See Load Diagram.
V
CC
= 5V+10%
Output Load
I/O Pin
166Ω
1.76V
30pF
Operation Truth Table
/CS
H
L
L
L
L
/OE /WE
X
L
H
L
H
X
H
L
L
H
Data Pins
High Impedence
Data Out
Data In
Data In
High Impedence
Supply Current
I
SB1
,I
SB2
I
CC1
I
CC1
I
CC1
I
SB1
,I
SB2
Mode
Standby
Read
Write
Write
High Z
Notes : H=V
IH
: L=V
IL
: X=V
IH
or V
IL
PAGE 4
Issue 5.0 June 1999
MOSAIC [ MOSAIC ]
