ISSUE 1.7 April 2001
SYS84000RKX - 85/10/12
Write Cycle No.2 Timing Waveform
(1,5)
t
WC
Address
t
AS(6)
t
CW
t
WR(7)
CS
t
AW
t
WP(2)
WE
t
WHZ(3,9)
t
OW
High-Z
t
DW
t
OH
(8)
(4)
Don't
Care
Dout
High-Z
t
DH
Din
Data Valid
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS and WE low.
(3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes.
(7) CS or WE must be high during address transitions.
(8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Data Retention Waveform
Vcc
4.5V
DATA RETENTION MODE
4.5V
t
CDR
2.2V
t
R
2.2V
V
DR
CS > Vcc -0.2V
0V
CS
6
MOSAIC [ MOSAIC ]
