ISSUE 5.0 November 1999
SYS8512FKX-70/85/10/12
Write Cycle No.2 Timing Waveform
t
WC
Address
t
AS (3)
t
CW (2)
t
WR (4)
CS
t
AW
t
WP (1)
WE
t
WHZ(5)
t
OW
High-Z
t
DW
t
OH
(7)
(8)
Don't
Care
Dout
High-Z
t
DH
Din
AC Characteristics Notes
(1) A write occurs during the overlap (t
WP
) of a low CS and a low WE.
(2) t
CW
is measured from the earlier of CS or WE going high to the end of write cycle.
(3) t
AS
is measured from the address valid to the beginning of write.
(4) t
WR
is measured from the earliest of CS or WE going high to the end of write.
(5) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(6) If CS goes low simultaneously with WE going low or after WE going low , outputs remain in a high impedance state.
(7) D
OUT
is in the same phase as written data of this write cycle.
(8) D
OUT
is the read data of next address.
(9) If CS is low during this period, I/O pins are in the output state, and inputs out of phase must not be applied to I/O pins.
(10) This parameter is sampled and not 100% tested.
(11) t
WHZ
is defined as the time at which the outputs achieve open circuit conditions and is not referenced to output voltage
levels. This parameter is sampled and not 100% tested.
Data Retention Waveform
Vcc
DATA RETENTION MODE
4.5V
4.5V
t
CDR
2.2V
t
R
2.2V
V
DR
CS > Vcc -0.2V
0V
CS
6
MOSAIC [ MOSAIC ]
