SYS88000RKX - 85/10/12
ISSUE 1.5 : April 2001
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
I/O Pin
645
Ω
1.76V
100pF
Operation Truth Table
CS
H
L
L
L
L
OE
X
L
L
H
H
WE
X
L
H
L
H
DATA PINS
High Impedance
Invalid State
Data Out
Data In
High-Impedance
SUPPLY CURRENT
I
SB1
, I
SB2
, I
SB3
, I
SB4
~
I
CC1
I
CC1
I
CC1
MODE
Standby
Invalid
Read
Write
High-Z
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
OE must not be tied low permanently.
Low V
cc
Data Retention Characteristics - L Version Only
Parameter
Symbol
Test Condition
CS > V
CC
-0.2V
V
CC
= 3.0V, CS > V
CC
-0.2V
See Retention Waveform
See Retention Waveform
min
2.0
-
0
5.0
typ
(1)
-
-
-
-
max
-
2
-
-
Unit
V
mA
ns
ms
V
CC
for Data Retention
V
DR
Data Retention Current
I
CCDR1 (2)
Chip Deselect to Data Retention Time t
CDR
Operation Recovery Time
t
R
Notes
(1)
Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
(3) Add 840mA to -L CMOS standby currents to obtain industrial temp range parameters.
3
MOSAIC [ MOSAIC ]
