ISSUE 1.5 : April 2001
SYS88000RKX - 85/10/12
AC OPERATING CONDITIONS
Read Cycle
-85
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
-10
max
-
85
85
50
-
-
-
5
5
-12
max
-
100
100
55
-
-
-
5
5
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
85
-
-
-
11.5
1.5
1.5
0
0
min
100
-
-
-
11.5
1.5
1.5
0
0
min
120
-
-
-
11.5
1.5
1.5
0
0
max
-
120
120
60
-
-
-
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-85
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
***
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write ***
-10
max
-
-
-
-
-
-
35
-
-
-
-12
max
-
-
-
-
-
-
40
-
-
-
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
85
75
75
0
60
5
0
40
0
5
min
100
80
80
0
70
5
0
45
0
5
min
120
100
100
0
70
5
0
45
0
5
max
-
-
-
-
-
-
40
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*** Theses signals are the internal Ram signals on the module and are included to assist control signal
timing.
4
MOSAIC [ MOSAIC ]
