MOSEL VITELIC
Serial Presence Detect Information
A serial presence detect storage device –
2
PROM – is assembled onto the module. Informa-
E
tion about the module configuration, speed, etc. is
V437216C04VDTG-10PC
written into the E
2
PROM device during module pro-
duction using a serial presence detect protocol (I
2
C
synchronous 2-wire bus)
SPD-Table for -10PC modules:
Hex Value
Byte Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function Described
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x4 SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (continued)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay from Back to Back Random
Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
Maximum Data Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at CL = 1
Minimum Row Precharge Time
Minimum Row Active to Row Active Delay t
RRD
Minimum RAS to CAS Delay t
RCD
Minimum RAS Pulse Width t
RAS
SPD Entry Value
128
256
SDRAM
12
10
1
72
0
LVTTL
10.0 ns
6.0 ns
ECC
Self-Refresh, 15.8
µ
s
x4
x4
t
ccd
= 1 CLK
1, 2, 4, 8, full page
4
CL = 2, 3
CS Latency = 0
WL = 0
Registered/Buffered
Vcc tol ± 10%
10.0 ns
6.0 ns
Not Supported
Not Supported
20 ns
16 ns
20 ns
45 ns
16Mx72
80
08
04
0C
0A
01
48
00
01
A0
60
02
80
04
04
01
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
8F
04
06
01
01
1F
0E
A0
60
00
00
14
10
14
2D
V437216C04VDTG-10PC Rev. 1.3 July 2001
4
MOSEL [ MOSEL VITELIC, CORP ]
