V437432S24V
Block Diagram
WE
CS0
DQM0
I/O1–I/O8
10
DQM1
I/O9–I/O16
10
BC0–7
10
CS2
DQM2
I/O17–I/O24
10
DQM3
I/O25–I/O32
10
E
2
PROM SPD (256 WORD X 8 BITS)
SCL0
SA2
SA1
SA0
SDA
WP
47K
CILETIV LESOM
V
MOSEL VITELIC
MANUFACTURED
Module Part Number Information
4
3
74
32
S
2
4
V
X
T
G - XX
SPEED
75PC = PC133 CL3,2
75 = PC133 CL3
10PC = PC133 CL3,2
LEAD FINISH
G = GOLD
SDRAM
3.3V
WIDTH
DEPTH
168 PIN Unbuffered
DIMM X8 COMPONENT
REFRESH
RATE 8K
COMPONENT
PACKAGE, T = TSOP
COMPONENT A=0.17u B=0.14u
REV LEVEL
LVTTL
4 BANKS
DQM WE
I/O1–I/O8
DQM WE
I/O1–I/O8
DQM WE
I/O1–I/O8
CS
D0
CS
D1
CS
DQM4
I/O40–I/O33
10
DQM5
I/O48–I/O41
10
DQM WE
I/O1–I/O8
DQM WE
I/O1–I/O8
CS
D4
CS
D5
WE
DQM
I/O1–I/O8
WE
DQM
I/O1–I/O8
CS
D2
CS
D3
DQM6
I/O49–I/O56
10
DQM7
I/O57–I/O64
10
CKE0
RAS
CAS
WE
A(11:0)
BA0, BA1
WE
DQM
I/O1–I/O8
WE
DQM
I/O1–I/O8
CS
D6
CS
D7
CKE: SDRAM D0-D7
RAS: SDRAM D0-D7
CAS: SDRAM D0-D7
WE: SDRAM D0-D7
A(11:0): SDRAM D0-D7
BA0, BA1: SDRAM D0-D7
D0-D7
C0-C17
D0-D7
CLOCK WIRING
CLOCK INPUT
CLK0
CLK1
CLK2
CLK3
LOAD
5 SDRAM
Termination
4 SDRAMS +3.3pF Cap
Termination
V
CC
V
SS
V437432S24V Rev. 1.0 January 2002
3
MOSEL [ MOSEL VITELIC, CORP ]
