V437464E24V
CILETIV LESOM
# Symbol Parameter
Clock and Clock Enable
1
t
CK
2
f
CK
3
t
AC
4
5
6
7
8
9
10
t
CH
t
CL
t
CS
t
CH
t
CKSP
t
CKSR
t
T
AC Characteristics
3,4
T
A
= 0° to 70°C; V
SS
= 0V; V
CC
= 3.3V
±
0.3V, t
T
= 1 ns
Limit Values
-75PC
Min.
Max.
Min.
-75
Max.
-10PC
Min.
Max.
Unit
Note
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
System frequency
CAS Latency = 3
CAS Latency = 2
Clock Access Time
CAS Latency = 3
CAS Latency = 2
Clock High Pulse Width
Clock Low Pulse Width
Input Setup time
Input Hold Time
CKE Setup Time (Power down mode)
CKE Setup Time (Self Refresh Exit)
Transition time (rise and fall)
7.5
7.5
–
–
–
–
2.5
2.5
1.5
0.8
2.5
8
1
133
133
5.4
6
–
–
–
–
–
–
–
7.5
10
–
–
–
–
2.5
2.5
1.5
0.8
2
8
1
133
100
5.4
6
–
–
–
–
–
–
–
10
10
–
–
–
–
3
3
2
1
2
8
1
100
100
6
6
–
–
–
–
–
–
–
ns
ns
MHz
MHz
4,5
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
6
7
7
8
9
Common Parameters
11
12
13
14
15
16
t
RCD
t
RC
t
RAS
t
RP
t
RRD
t
CCD
RAS to CAS delay
Cycle Time
Active Command Period
Precharge Time
Bank to Bank Delay Time
CAS to CAS delay time
(same bank)
15
60
42
20
16
1
–
120k
–
–
–
–
20
70
45
20
15
1
–
120k
–
–
–
–
20
70
45
20
20
1
–
120k
–
–
–
–
ns
ns
ns
ns
ns
CLK
Refresh Cycle
17
18
t
SREX
t
REF
Self Refresh Exit Time
Refresh Period (8192 cycles)
10
64
–
–
10
64
–
–
10
64
–
–
ns
ms
9
8
Read Cycle
19
20
21
22
t
OH
t
LZ
t
HZ
t
DQZ
Data Out Hold Time
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
3
0
3
2
–
–
7.5
–
3
0
3
2
–
–
7.5
–
3
0
3
2
–
–
8
–
ns
ns
ns
CLK
10
4
Write Cycle
23
24
25
t
DPL
t
DAL
t
DQW
Data input to Precharge (write recovery)
Data In to Active/refresh
DQM Write Mask Latency
2
5
0
–
–
–
2
5
0
–
–
–
1
5
0
–
–
–
CLK
CLK
CLK
11
V437464E24V Rev. 1.0 January 2002
9
MOSEL [ MOSEL VITELIC, CORP ]
