V437464Q24V
SPD-Table for modules: (Continued)
Hex Value
Byte Num-
ber
Function Described
SPD Entry Value
-75PC
-75
-10PC
28
Minimum Row Active to Row Active Delay
tRRD
14 ns/15 ns/16 ns
0E
0F
10
29
30
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
15 ns/20 ns
42 ns/45 ns
512 MByte
1.5 ns/2 ns
0.8 ns/1 ns
1.5 ns/2 ns
0.8 ns/1 ns
14
2D
80
15
08
15
08
00
14
2D
80
15
08
15
08
00
14
2D
80
20
10
20
10
00
31
32
33
SDRAM Input Hold Time
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
35
36-61
Superset Information (May be used in Fu-
ture)
62
63
SPD Revision
Revision 2/1.2
Mosel Vitelic
02
46
40
00
02
8B
40
00
12
F9
40
00
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
64
65-71
72
73-90
91-92
93
Module Part Number (ASCII)
PCB Identification Code
V437464Q24V
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
Reserved
94
95-98
99-125
126
00
64
00
64
00
64
Intel Specification for Frequency
Detailed Information
100 MHz
127
128+
Unused Storage Location
00
08
08
V437464Q24V Rev. 1.0 January 2002
6
MOSEL [ MOSEL VITELIC, CORP ]
