MOSEL VITELIC
V53C516400A
4M x 4 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C516400A
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
50
50 ns
25 ns
35 ns
84 ns
60
60 ns
30 ns
40 ns
104 ns
Features
s
4M x 4-bit organization
s
Fast Page Mode for a sustained data rate
of 50 MHz
s
RAS access time: 50, 60 ns
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh and Hidden Refresh
s
Refresh Interval: 4096 cycles/64 ms
s
Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
s
Single +5V
±
10% Power Supply
s
TTL Interface
Description
The V53C516400A is a 4,194,304 x 4 bit high-
performance CMOS dynamic random access mem-
ory. The V53C516400A offers Page mode opera-
tion. The V53C516400A has asymmetric address,
12-bit row and 10-bit column.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 1024 x 4 bits,
within a page, with cycle times as short as 35ns.
These features make the V53C516400A ideally
suited for a wide variety of high performance com-
puter systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
Package Outline
K
•
Access Time (ns)
50
•
Power
Std.
•
T
•
60
•
Temperature
Mark
Blank
V53C516400A Rev. 1.1 March 1998
1
MOSEL [ MOSEL VITELIC, CORP ]
