MO SEL VITELIC
V53C808H
Waveforms of Self Refresh Cycle (Optional)
t
RP (3)
t
RASS (54)
t
RPS (57)
V
IH
RAS
t
RPC (48)
V
IL
t
RPC (48)
t
t
CSR (47)
CP (43)
t
CHS (56)
t
CHD (57)
V
IH
UCAS, LCAS
ADDRESS
V
IL
V
IH
V
IL
V
OH
I/O
WE
OE
OPEN
V
OL
V
IH
V
IL
V
IH
V
IL
808H-17
Functional Description
Read Cycle
The V53C808H is a CMOS dynamic RAM opti-
mized for high data bandwidth, low power applica-
tions. It is functionally similar to a traditional
dynamic RAM. The V53C808H reads and writes
data by multiplexing an 20-bit address into a 10-bit
row and a 10-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS opera-
tion. The column address must be held for a mini-
mum specified by t . Data Out becomes valid only
AR
when t
, t
, t
and t
are all satisifed. As
OAC RAC CAA
CAC
a result, the access time is dependent on the timing
relationships between these parameters. For exam-
ple, the access time is limited by t
when t
,
CAA
RAC
t
and t
are all satisfied.
CAC
OAC
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column ad-
dress is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be end-
ed or aborted before the minimum t
time has ex-
RAS
pired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time t /t has elapsed.
RP CP
the high state and t
must be satisfied.
OED
V53C808H Rev. 1.5 April 1998
14
MOSEL [ MOSEL VITELIC, CORP ]
