V54C3128(16/80/40)4V(T/S)
x8 Configuration
Column Addresses
A0 - A9, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Block Diagram
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Bank 0
Bank 1
Bank 2
Column decoder
Sense amplifier & I(O) bus
RAS
CKE
CAS
WE
CS
V54C3128(16/80/40)4V(T/S) Rev. 1.2 August 2002
7
DQM
CLK
CILETIV LESOM
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Bank 3
4096 x 1024
x 8 bit
4096 x 1024
x 8 bit
4096 x 1024
x 8 bit
4096 x 1024
x 8 bit
Input buffer
Output buffer
Control logic & timing generator
I/O
1
-I/O
8