欢迎访问ic37.com |
会员登录 免费注册
发布采购

V54C316162V-7 参数 Datasheet PDF下载

V54C316162V-7图片预览
型号: V54C316162V-7
PDF下载: 下载PDF文件 查看货源
内容描述: 200/183/166/143 MHz的3.3伏, 4K刷新超高性能1M ×16 SDRAM 2组X达512Kbit ×16 [200/183/166/143 MHz 3.3 VOLT, 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16]
分类和应用: 动态存储器
文件页数/大小: 21 页 / 306 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
 浏览型号V54C316162V-7的Datasheet PDF文件第6页浏览型号V54C316162V-7的Datasheet PDF文件第7页浏览型号V54C316162V-7的Datasheet PDF文件第8页浏览型号V54C316162V-7的Datasheet PDF文件第9页浏览型号V54C316162V-7的Datasheet PDF文件第11页浏览型号V54C316162V-7的Datasheet PDF文件第12页浏览型号V54C316162V-7的Datasheet PDF文件第13页浏览型号V54C316162V-7的Datasheet PDF文件第14页  
V54C316162V  
AC Characteristics (1,2,3)  
T = 0 to 70°C; V = 0 V; V = 3.3 V ± 0.3 V, t = 1 ns  
A
SS  
CC  
T
Limit Values  
-55  
-5  
-6  
-7  
#
Symbol Parameter  
Min.  
Max.  
Min. Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
Clock and Clock Enable  
1
2
3
tCK  
tCK  
tAC  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
5
5.5  
10  
6
7
ns  
ns  
10  
10  
10  
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
200  
100  
183  
100  
166  
100  
143  
100  
MHz  
MHz  
Access Time from Clock  
CAS Latency = 3  
5
7
5.3  
7
5.5  
7
5.5  
7
ns  
ns  
2
3
CAS Latency = 2  
4
5
6
tCH  
tCL  
tT  
Clock High Pulse Width  
Clock Low Pulse Width  
Transition time  
2.5  
2.5  
1
2.5  
2.5  
1
2.5  
2.5  
1
2.5  
2.5  
1
ns  
ns  
ns  
10  
10  
10  
10  
Setup and Hold Times  
7
8
9
tCMDS  
tAS  
Command Setup Time  
Address Setup Time  
Data In Setup Time  
CKE Setup Time  
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4
4
4
4
4
4
4
4
tDS  
10 tCKS  
11 tCMDH  
12 tAH  
Command Hold Time  
Address Hold Time  
Data In Hold Time  
CKE Hold Time  
13 tDH  
14 tCKH  
Common Parameters  
15 tRCD  
16 tRAS  
17 tRC  
18 tRP  
19 tRRD  
Row to Column Delay Time  
15  
40  
60  
15  
10  
16.5  
45  
18  
48  
66  
18  
12  
18  
48  
70  
21  
14  
ns  
ns  
ns  
ns  
ns  
5
5
5
5
5
Row Active Time  
Row Cycle Time  
100K  
100K  
100K  
100K  
63  
Row Precharge Time  
17  
Activate(a) to Activate(b) Com-  
11  
mand  
period  
20 tCCD  
CAS(a) to CAS(b) Command pe-  
riod  
1
1
1
1
CLK  
21 tRCS  
22 tSB  
Mode Register Set-up time  
10  
0
11  
0
12  
0
14  
0
ns  
ns  
Power Down Mode Entry Time  
5
5.5  
6
7
Refresh Cycle  
23 tREF  
Refresh Period (4096 cycles)  
64  
64  
64  
64  
ms  
V54C316162V Rev.2.9 September 2001  
10