V54C3256(16/80/40)4V(T/S/B)
V 54 C 3 25616 4 V A L T
Mosel Vitelic
Manufactured
Speed
6 ns
Device
7 ns
8 ns
Number
SYNCHRONOUS
DRAM FAMILY
Special
Feature
TSOP Component
Package
C=CMOS Family
3.3V, LVTTL INTERFACE
16Mx16(8K Refresh)
Description Pkg.
Pin Count
L=Low Power
TSOP-II
T
54
4 Banks
Component Rev Level A=0.17um
B=0.14um
V=LVTTL
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK
Clock Input
CKE
Clock Enable
V
I/O
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
I/O
V
I/O
I/O
V
I/O
I/O
V
I/O
I/O
V
I/O
V
NC
UDQM
CLK
CKE
A12
CS
Chip Select
CC
1
SS
16
SSQ
15
14
CCQ
13
12
SSQ
11
10
RAS
Row Address Strobe
Column Address Strobe
Write Enable
V
V
V
V
CCQ
I/O
I/O
3
SSQ
I/O
I/O
5
CCQ
I/O
2
CAS
WE
4
A0–A12
BA0, BA1
I/O1–I/O16
LDQM, UDQM
VCC
Address Inputs
Bank Select
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
6
I/O
7
SSQ
Data Input/Output
Data Mask
CCQ
9
SS
I/O
8
V
CC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
Power (+3.3V)
Ground
VSS
VCCQ
VSSQ
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
A11
A
A
A
A
A
A
V
9
8
7
6
5
4
SS
10
NC
A
0
A
1
A
2
A
3
V
CC
356164V-01
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
3
MOSEL [ MOSEL VITELIC, CORP ]
