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V58C2256404S 参数 Datasheet PDF下载

V58C2256404S图片预览
型号: V58C2256404S
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能2.5伏256兆位的DDR SDRAM [HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 61 页 / 810 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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V58C2256(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
6
DDR333B
7
DDR266A
7.5ns
7ns
143 MHz
75
DDR266B
10 ns
7.5 ns
133 MHz
PRELIMINARY
Features
High speed data transfer rates with system
frequency up to 166 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 66-pin 400 mil TSOP or 60 Ball SOC
BGA
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with
CK transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
QFC options for FET control. x4 parts.
*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing
DDR 266A Supports PC2100 module with 2-2-2 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
CILETIV LESO M
8
DDR200
10 ns
8 ns
125 MHz
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
System Frequency (f
CK max
)
7.5 ns
6 ns
166 MHz
Description
The V58C2256(804/404/164)S is a four bank
DDR DRAM organized as 4 banks x 8Mbit x 8 (804),
4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4
(404). The V58C2256(804/404/164)S achieves high
speed data transfer rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 SOC BGA
CK Cycle Time (ns)
-6
Power
-8
-7
-75
Std.
L
Temperature
Mark
Blank
V58C2256(804/404/164)S Rev.1.4 October 2002
1