V62C1801024L(L)
Ultra Low Power
128K x 8 CMOS SRAM
Features
• Ultra Low-power consumption
- Active: 20mA at 70ns
- Stand-by: 5
µ
A
(CMOS input/output)
1
µ
A
CMOS input/output, L version
• Single +1.8V to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1 , CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
Functional Description
The V62C1801024L is a low power CMOS Static RAM or-
ganized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW CE1 , an active HIGH CE2, an
active LOW OE, and Tri-state I/O’s. This device has an a-
utomatic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1 ) with Write Enable (WE) LOW, and Chip Ena-
ble 2 (CE2) HIGH. Reading from the device is performed by
taking Chip Enable 1 (CE1) with Output Enable (OE)
LOW while Write Enable (WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance st-
ate when the device is deselected: the outputs are disabled
during a write cycle.
The V62C1801024LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1801024L is available in
a 32-pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP
(See next page)
A
11
A
9
A
8
A
13
WE
CE
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
A
0
INPUT
BUFFER
BUFFER
ROW DECODER
ROW DECODER
SENSE AMP
SENSE AMP
A
1
A
1
A
2
A
2
A
3
A
4
A
3
A
5
A
4
A
6
A
5
A
7
A
6
A
8
A
7
A
9
I/O8
I/O
7
A
15
Vcc
NC
A
16
A
14
A
12
1024
1024
X
X
1024
1024
I/O1
A
7
A
6
A
5
A
4
I/O
0
A
8
COLUMN DECODER
COLUMN DECODER
A
10
A
11
A
12
A
13
A
14
A
15
A
16
CONTROL
CIRCUIT
A
15
A
16
CONTROL
CIRCUIT
OE
WE
OE
CE1
WE
CE2
A
9
A
10
A
11
A
12
A
13
A
14
CE1
CE2
1
REV. 1.1
April
2001 V62C1801024L(L)
MOSEL [ MOSEL VITELIC, CORP ]
