V62C21164096
256K x 16, 0.20
µm
CMOS STATIC RAM
PRELIMINARY
s
s
s
s
s
s
s
s
CILETIV LESOM
Features
A
0
A
6
A
7
A
8
A
9
I/O
1
I/O
16
UBE
LBE
OE
WE
CE
1
CE
2
Description
The V62C21164096 is a 4,194,304-bit static
random-access memory organized as 262,144
words by 16 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing with
common system bus structures.
High-speed: 70, 85 ns
Ultra low CMOS standby current of 4µA (max.)
Fully static operation
All inputs and outputs directly TTL compatible
Three state outputs
Ultra low data retention current (V
CC
= 1.2V)
Operating voltage: 2.3V – 3.0V
Packages
– 44-pin TSOP (Standard)
– 48-Ball CSP BGA (8mm x 10mm)
Functional Block Diagram
V
CC
Row
Decoder
1024 x 4096
Memory Array
GND
Column I/O
Input
Data
Circuit
Column Decoder
A
10
A
17
Control
Circuit
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
–40°C to +85°C
Package Outline
T
•
•
B
•
•
Access Time (ns)
70
•
•
85
•
•
L
•
Power
LL
•
•
Temperature
Mark
Blank
I
V62C21164096 Rev. 1.6 October 2001
1