MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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DSP56002/D, Rev. 3
DSP56002
24-BIT DIGITAL SIGNAL PROCESSOR
The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an
efficient 24-bit DSP core, program and data memories, various peripherals, and support
circuitry. The DSP56000 core is fed by on-chip Program RAM, and two independent data RAMs.
The DSP56002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI),
parallel Host Interface (HI), Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip
Emulation (OnCE™) port. This combination of features, illustrated in
, makes the
DSP56002 a cost-effective, high-performance solution for high-precision general purpose digital
signal processing.
1
6
3
15
16-bit Bus
24-bit Bus
Program
Memory
512
×
24 RAM
64
×
24 ROM
(boot)
X Data
Memory
256
×
24 RAM
256
×
24 ROM
(A-law/
µ-law)
Y Data
Memory
256
×
24 RAM
256
×
24 ROM
(sine)
24-bit
Timer/
Event
Counter
Sync.
Serial
(SSI)
or I/O
Serial
Comm.
(SCI)
or I/O
Host
Interface
(HI)
or I/O
24-bit
56000 DSP
Core
Internal
Data
Bus
Switch
OnCE™
Port
PLL
Clock
Gen.
7
4
Address
Generation
Unit
PAB
XAB
YAB
GDB
PDB
XDB
YDB
External
Address
Bus
Switch
Address
16
External
Data
Bus
Switch
Data
24
Interrupt
Control
Program
Decode
Controller
Program
Address
Generator
Data ALU
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
Bus
Control
Control
10
Program Control Unit
3
IRQ
AA0604
Figure 1
DSP56002 Block Diagram
©1996 MOTOROLA, INC.
MOTOROLA [ MOTOROLA, INC ]
