MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Binary to 1-8 Decoder (Low)
The MC10161 is designed to decode a three bit input word to a one of eight
line output. The selected output will be low while all other outputs will be high. The
enable inputs, when either or both are high, force all outputs high.
The MC10161 is a true parallel decoder. No series gating is used internally,
eliminating unequal delay times found in other decoders. This design provides
the identical 4 ns delay from any address or enable input to any output.
A complete mux/demux operation on 16 bits for data distribution is illustrated
in Figure 1. This system, using the MC10136 control counters, has the
capability of incrementing, decrementing or holding data channels. When both
S0 and S1 are low, the index counters reset, thus initializing both the mux and
demux units. The four binary outputs of the counter are buffered by the
MC10101s to send twisted–pair select data to the multiplexer/demultiplexer to
units.
PD = 315 mW typ/pkg (No Load)
tpd = 4.0 ns typ
tr, tf = 2.0 ns typ (20%–80%)
MC10161
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
E0 2
E1 15
6 Q0
5 Q1
4 Q2
A 7
3 Q3
13 Q4
B 9
12 Q5
11 Q6
C 14
10 Q7
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
E0
Q3
Q2
Q1
Q0
A
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
E1
C
Q4
Q5
Q6
Q7
B
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
TRUTH TABLE
ENABLE
INPUTS
E1
L
L
L
L
L
L
L
L
H
X
E0
L
L
L
L
L
L
L
L
X
H
INPUTS
C
L
L
L
L
H
H
H
H
X
X
B
L
L
H
H
L
L
H
H
X
X
A
L
H
L
H
L
H
L
H
X
X
Q0
L
H
H
H
H
H
H
H
H
H
Q1
H
L
H
H
H
H
H
H
H
H
Q2
H
H
L
H
H
H
H
H
H
H
OUTPUTS
Q3
H
H
H
L
H
H
H
H
H
H
Q4
H
H
H
H
L
H
H
H
H
H
Q5
H
H
H
H
H
L
H
H
H
H
Q6
H
H
H
H
H
H
L
H
H
H
Q7
H
H
H
H
H
H
H
L
H
H
3/93
©
Motorola, Inc. 1996
3–73
REV 5
MOTOROLA [ MOTOROLA, INC ]
