欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC10E141FN 参数 Datasheet PDF下载

MC10E141FN图片预览
型号: MC10E141FN
PDF下载: 下载PDF文件 查看货源
内容描述: 8位移位寄存器 [8-BIT SHIFT REGISTER]
分类和应用: 移位寄存器
文件页数/大小: 4 页 / 115 K
品牌: MOTOROLA [ MOTOROLA, INC ]
 浏览型号MC10E141FN的Datasheet PDF文件第2页浏览型号MC10E141FN的Datasheet PDF文件第3页浏览型号MC10E141FN的Datasheet PDF文件第4页  
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8 Bit Shift Register
The MC10E/100E141 is an 8-bit full-function shift register. The E141
performs serial/parallel in and serial/parallel out, shifting in either
direction. The eight inputs D0 – D7 accept parallel input data, while
DL/DR accept serial input data for left/right shifting. The Qn outputs do
not need to be terminated for the shift operation to function. To minimize
noise and power, any Q output not used should be left unterminated.
MC10E141
MC100E141
8-BIT SHIFT
REGISTER
700MHz Min. Shift Frequency
8-Bit
Full-Function, Bi-Directional
Asynchronous Master Reset
Pin-Compatible with E241
Extended 100E VEE Range of – 4.2V to – 5.46V
75kΩ Input Pulldown Resistors
The select pins, SEL0 and SEL1, select one of four modes of
operation: Load, Hold, Shift Left, Shift Right, according to the Function
Table.
Input data is accepted a set-up time before the positive clock edge. A
HIGH on the Master Reset (MR) pin asynchronously resets all the
registers to zero.
Pinout: 28-Lead PLCC
(Top View)
SEL0
25
SEL1
CLK
MR
VEE
DR
D0
D1
26
27
28
1
2
3
4
5
D2
6
D3
7
D4
8
VCCO
9
Q0
10
Q1
11
Q2
DL
24
D7
23
D6
22
D5
21
VCCO
20
Q7
19
18
17
16
15
14
13
12
Q6
Q5
VCC
NC
VCCO
Q4
Q3
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
FUNCTION TABLE
SEL0
L
L
H
H
SEL1
L
H
L
H
Function
Load
Shift Right (Dn to Dn+1)
Shift Left (Dn to Dn –1)
Hold
PIN NAMES
Pin
D0 – D7
DL, DR
SEL0, SEL1
CLK
Q0 – Q7
MR
Function
Parallel Data Inputs
Serial Data Inputs
Mode Select In Inputs
Clock
Data Outputs
Master Reset
* All VCC and VCCO pins are tied together on the die.
EXPANDED FUNCTION TABLE
Function
Load
Shift Right
Shift Left
Hold
Reset
7/96
DL
X
X
X
L
H
X
X
X
DR
X
L
H
X
X
X
X
X
SEL0
L
L
L
H
H
H
H
X
SEL1
L
H
H
L
L
H
H
X
MR
L
L
L
L
L
L
L
H
CLK
Z
Z
Z
Z
Z
Z
Z
X
Q0
D0
L
H
L
Q0
Q0
Q0
L
Q1
D1
Q0
L
Q0
Q1
Q1
Q1
L
Q2
D2
Q1
Q0
Q1
Q2
Q2
Q2
L
Q3
D3
Q2
Q1
Q2
Q3
Q3
Q3
L
Q4
D4
Q3
Q2
Q3
Q4
Q4
Q4
L
Q5
D5
Q4
Q3
Q4
Q5
Q5
Q5
L
Q6
D6
Q5
Q4
Q5
L
L
L
L
Q7
D7
Q6
Q5
L
H
H
H
L
©
Motorola, Inc. 1996
2–1
REV 3